- Generated on Wed Mar 29 2023 00:00:55 by
1.9.1
Timer device configuration. More...
Timer device configuration.
Timer configuration data.
Configuration type of a timer device timer_conf_t::dev, having timer_conf_t::ch_numof number of channels, each one modeled as timer_channel_conf_t.
Timer configuration options.
Override resolution options.
Timer configuration.
All timers can be derived from TC0_t struct. Need check at runtime the type and number of channels to perform all operations.
General purpose timers (GPT[0-3]) are configured consecutively and in order (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
Define timer configuration values
Definition at line 260 of file periph_cpu.h.
#include <periph_cpu.h>
Data Fields | |
| TC0_t * | dev |
| Pointer to the used as Timer device. More... | |
| pwr_reduction_t | pwr |
| Power Management. | |
| timer_type_t | type |
| Timer Type. | |
| cpu_int_lvl_t | int_lvl [TIMER_CH_MAX_NUMOF] |
| Interrupt channels level. | |
| uint_fast8_t | chn |
| number of channels | |
| uint_fast8_t | cfg |
| timer config word | |
| timer_dev_t | prescaler |
| the lower neighboring timer (not initialized for LETIMER) | |
| timer_dev_t | timer |
| the higher numbered timer | |
| IRQn_Type | irq |
| number of the higher timer IRQ channel | |
| uint8_t | channel_numof |
| number of channels per timer | |
| TIMER_Type * | dev |
| timer device More... | |
| uint32_t | max |
| maximum value to count to (16/32 bit) More... | |
| uint32_t | rcu_mask |
| corresponding bit in the RCC register | |
| uint8_t | bus |
| APBx bus the timer is clock from. | |
| uint8_t | irqn |
| global IRQ channel More... | |
| uint32_t | dev |
| Address of timer base. | |
| int | irqn |
| Number of the higher timer IRQ channel. | |
| uint32_t | sysctl |
| Address of timer system control. | |
| uint32_t | intbase |
| Interrupt base of timer. | |
| int | channels |
| Number of channels for the timer. | |
| NRF_TIMER_Type * | dev |
| timer device | |
| uint8_t | channels |
| number of hardware channels minus one More... | |
| uint8_t | bitmode |
| counter width | |
| const timer_channel_conf_t * | ch |
| pointer to timer channel configuration | |
| uint8_t | ch_numof |
| number of timer channels | |
| Tc * | dev |
| timer device | |
| uint8_t | id_ch0 |
| ID of the timer's first channel. | |
| TIM_TypeDef * | dev |
| timer device | |
| uint32_t | rcc_mask |
| corresponding bit in the RCC register | |
| uint8_t timer_conf_t::channels |
number of hardware channels minus one
The last hardware channels is implicitly used by timer_read() and not available to the user. This value, hence, is the number of channels available to the user.
Definition at line 197 of file periph_cpu_common.h.
| TIMER_Type * timer_conf_t::dev |
Pointer to the used as Timer device.
pointer to timer base address
Definition at line 261 of file periph_cpu.h.
| TIMER_Type* timer_conf_t::dev |
| uint8_t timer_conf_t::irqn |
| uint32_t timer_conf_t::max |
maximum value to count to (16/32 bit)
Max tick value of timer.
Definition at line 258 of file periph_cpu.h.
1.9.1