Structure describing the memory layout of the registers of a GPIO port on ATmega MCUs. More...

Detailed Description

Structure describing the memory layout of the registers of a GPIO port on ATmega MCUs.

Definition at line 125 of file periph_cpu_common.h.

Data Fields
volatile uint8_t	pin
	Toggle bits in the port register.

volatile uint8_t	ddr
	Configure pins as output (1) or input (0) using the Data Direction Register.

volatile uint8_t	port
	Read/write the state of GPIO pins using the Port Data Register.

Field Documentation

volatile uint8_t atmega_gpio_port_t::ddr

Configure pins as output (1) or input (0) using the Data Direction Register.

Definition at line 139 of file periph_cpu_common.h.

volatile uint8_t atmega_gpio_port_t::pin

Toggle bits in the port register.

Note: The bits in the port register will be also toggled for inputs. This can be both a footgun as well as an efficient way to toggle the pull up resistor on inputs

Referred to as "Input Pins Address" in the datasheet.

Definition at line 134 of file periph_cpu_common.h.

volatile uint8_t atmega_gpio_port_t::port

Read/write the state of GPIO pins using the Port Data Register.

Note: When in input mode (see atmega_gpio_port_t::ddr) writing a 1 will enable the pull up resistor, writing a 0 will put the pin in floating mode.

Definition at line 147 of file periph_cpu_common.h.

The documentation for this struct was generated from the following file: