I2C registers. More...
I2C registers.
Definition at line 27 of file cc26xx_cc13xx_i2c.h.
#include <cc26xx_cc13xx_i2c.h>
Data Fields | ||
| reg32_t | SOAR | |
| slave own address | ||
| union { | ||
| reg32_t SSTAT | ||
| slave status More... | ||
| reg32_t SCTL | ||
| slave control More... | ||
| }; | ||
| reg32_t | SDR | |
| slave data | ||
| reg32_t | SIMR | |
| slave interrupt mask | ||
| reg32_t | SRIS | |
| slave raw interrupt status | ||
| reg32_t | SMIS | |
| slave masked interrupt status | ||
| reg32_t | SICR | |
| slave interrupt clear | ||
| reg32_t | __reserved [0x1F9] | |
| meh | ||
| reg32_t | MSA | |
| master slave address | ||
| union { | ||
| reg32_t MSTAT | ||
| master status More... | ||
| reg32_t MCTRL | ||
| master control More... | ||
| }; | ||
| reg32_t | MDR | |
| master data | ||
| reg32_t | MTPR | |
| master timer period | ||
| reg32_t | MIMR | |
| master interrupt mask | ||
| reg32_t | MRIS | |
| master raw interrupt status | ||
| reg32_t | MMIS | |
| master masked interrupt statues | ||
| reg32_t | MICR | |
| master interrupt clear | ||
| reg32_t | MCR | |
| master configuration | ||
| reg32_t i2c_regs_t::__reserved[0x1F9] |
meh
Definition at line 38 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MCR |
master configuration
Definition at line 50 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MCTRL |
master control
Definition at line 42 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MDR |
master data
Definition at line 44 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MICR |
master interrupt clear
Definition at line 49 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MIMR |
master interrupt mask
Definition at line 46 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MMIS |
master masked interrupt statues
Definition at line 48 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MRIS |
master raw interrupt status
Definition at line 47 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MSA |
master slave address
Definition at line 39 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MSTAT |
master status
Definition at line 41 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::MTPR |
master timer period
Definition at line 45 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SCTL |
slave control
Definition at line 31 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SDR |
slave data
Definition at line 33 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SICR |
slave interrupt clear
Definition at line 37 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SIMR |
slave interrupt mask
Definition at line 34 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SMIS |
slave masked interrupt status
Definition at line 36 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SOAR |
slave own address
Definition at line 28 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SRIS |
slave raw interrupt status
Definition at line 35 of file cc26xx_cc13xx_i2c.h.
| reg32_t i2c_regs_t::SSTAT |
slave status
Definition at line 30 of file cc26xx_cc13xx_i2c.h.