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periph_cpu_common.h
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1/*
2 * Copyright (C) 2015 HAW Hamburg
3 * 2016 Freie Universität Berlin
4 * 2016 INRIA
5 * 2023 Hugues Larrive
6 *
7 * This file is subject to the terms and conditions of the GNU Lesser
8 * General Public License v2.1. See the file LICENSE in the top level
9 * directory for more details.
10 */
11
25#ifndef PERIPH_CPU_COMMON_H
26#define PERIPH_CPU_COMMON_H
27
28#include "cpu.h"
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
38#define CPUID_LEN (4U)
41#ifndef DOXYGEN
46#define HAVE_GPIO_T
47typedef uint8_t gpio_t;
49#endif
50
54#define GPIO_UNDEF (0xff)
55
59#define GPIO_PIN(x, y) ((x << 4) | y)
60
66#if (defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)) \
67 || (defined(PUD) && (PUD != 4)) || (defined(INT0) && (INT0 == 6))
68 /* match with 65 devices against 61 for (PORTB == _SFR_IO8(0x18)) which
69 * did not work here anyway */
70#define GPIO_PORT_DESCENDENT
71#endif
72
73#ifdef GPIO_PORT_DESCENDENT
74#ifdef _AVR_ATTINY1634_H_INCLUDED
75/* the only one that requires particular treatment! */
76#define ATMEGA_GPIO_BASE_A (0x2F)
77#else
78/* all other port descendent, including :
79 - _AVR_IO8534_ (only have port A but with 0x1B address) ;
80 - _AVR_IOAT94K_H_ (only have ports D and E) ;
81 - _AVR_IOTN28_H_ (only have ports A and D). */
82#define ATMEGA_GPIO_BASE_A (0x39)
83#endif /* _AVR_ATTINY1634_H_INCLUDED */
84#else /* !GPIO_PORT_DESCENDENT */
85#define ATMEGA_GPIO_BASE_A (0x20)
86#endif /* GPIO_PORT_DESCENDENT */
92#define ATMEGA_GPIO_BASE_G (ATMEGA_GPIO_BASE_A + ATMEGA_GPIO_SIZE * ('G' - 'A'))
98#define ATMEGA_GPIO_BASE_H (0x100)
102#define ATMEGA_GPIO_SIZE (0x03)
103
104#if defined(DOXYGEN)
108#define GPIO_EXT_INT_NUMOF <CPU_SPECIFIC>
109#elif defined(INT7_vect)
110#define GPIO_EXT_INT_NUMOF (8U)
111#elif defined(INT6_vect)
112#define GPIO_EXT_INT_NUMOF (7U)
113#elif defined(INT5_vect)
114#define GPIO_EXT_INT_NUMOF (6U)
115#elif defined(INT4_vect)
116#define GPIO_EXT_INT_NUMOF (5U)
117#elif defined(INT3_vect)
118#define GPIO_EXT_INT_NUMOF (4U)
119#elif defined(INT2_vect)
120#define GPIO_EXT_INT_NUMOF (3U)
121#else
122#define GPIO_EXT_INT_NUMOF (2U)
123#endif
124
129typedef struct {
138 volatile uint8_t pin;
143 volatile uint8_t ddr;
151 volatile uint8_t port;
153
159static inline atmega_gpio_port_t *atmega_gpio_port(uint8_t port_num)
160{
161 static const uintptr_t base_addr = (uintptr_t)ATMEGA_GPIO_BASE_A;
162#ifdef GPIO_PORT_DESCENDENT
163 uintptr_t res = base_addr - port_num * sizeof(atmega_gpio_port_t);
164#else
165 uintptr_t res = base_addr + port_num * sizeof(atmega_gpio_port_t);
166#endif
167 /* GPIO ports up to (including) G are mapped in the I/O address space,
168 * port H and higher (if present) are mapped in a different contiguous
169 * region afterwards (e.g. 0x100 for ATmega2560). */
170#ifdef PORTH
171 if (port_num > 'G'-'A') {
172 static const uintptr_t offset = ATMEGA_GPIO_BASE_H - ATMEGA_GPIO_BASE_G;
173 res += offset;
174 }
175#endif
176
177 return (atmega_gpio_port_t *)res;
178}
179
180#ifndef DOXYGEN
190#define HAVE_GPIO_FLANK_T
191typedef enum {
192 GPIO_LOW,
193 GPIO_BOTH,
194 GPIO_FALLING,
195 GPIO_RISING,
198#endif /* ndef DOXYGEN */
199
200#ifndef DOXYGEN /* BEGIN: GPIO LL overwrites */
201#define HAVE_GPIO_SLEW_T
202typedef enum {
204 GPIO_SLEW_SLOW = 0,
205 GPIO_SLEW_FAST = 0,
208
209#define HAVE_GPIO_PULL_STRENGTH_T
210typedef enum {
212 GPIO_PULL_WEAK = 0,
216
217#define HAVE_GPIO_DRIVE_STRENGTH_T
218typedef enum {
220 GPIO_DRIVE_WEAK = 0,
224
225#define HAVE_GPIO_IRQ_TRIG_T
226typedef enum {
233
234#define HAVE_GPIO_STATE_T
235typedef enum {
243
244#define HAVE_GPIO_LL_PREPARE_WRITE_ALL_PINS
245#define HAVE_GPIO_LL_PREPARE_WRITE
246
247#endif /* END: GPIO LL overwrites */
248
253#define PERIPH_SPI_NEEDS_INIT_CS
254#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
255#define PERIPH_SPI_NEEDS_TRANSFER_REG
256#define PERIPH_SPI_NEEDS_TRANSFER_REGS
259#ifndef DOXYGEN
266#define SPI_MODE_SEL(pol, pha) ((pol << 3) | (pha << 2))
267
275#define HAVE_SPI_MODE_T
276typedef enum {
277 SPI_MODE_0 = SPI_MODE_SEL(0, 0),
278 SPI_MODE_1 = SPI_MODE_SEL(0, 1),
279 SPI_MODE_2 = SPI_MODE_SEL(1, 0),
280 SPI_MODE_3 = SPI_MODE_SEL(1, 1)
281} spi_mode_t;
290#define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
291
298#define HAVE_SPI_CLK_T
299typedef enum {
300 SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1),
301 SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0),
302 SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1),
303 SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0),
304 SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0)
305} spi_clk_t;
307#endif /* ifndef DOXYGEN */
308
323typedef struct {
325 gpio_t pin_ch[2];
327} pwm_conf_t;
333#define PERIPH_TIMER_PROVIDES_SET
334
338#define EEPROM_CLEAR_BYTE (0xff)
339
344#define NWDT_TIME_LOWER_LIMIT (1)
345#define NWDT_TIME_UPPER_LIMIT (8192U)
351#define WDT_HAS_STOP (1)
352
357#if defined(SCCR0) && !defined(RTT_BACKEND_SC)
358#define RTT_BACKEND_SC (1)
359#endif
360
361#if RTT_BACKEND_SC
362/* For MCU with MAC symbol counter */
363#ifndef RTT_MAX_VALUE
364#define RTT_MAX_VALUE (0xFFFFFFFFUL) /* 32-bit timer */
365#endif
366
367#ifndef RTT_FREQUENCY
368#define RTT_FREQUENCY (62500UL) /* in Hz. */
369#endif
370
371#else
372/* For MCU without MAC symbol counter */
373#ifndef RTT_MAX_VALUE
374#define RTT_MAX_VALUE (0x00FFFFFF) /* 24-bit timer */
375#endif
376/* possible values: 32, 128, 256, 512, 1024, 4096, 32768 */
377#ifndef RTT_FREQUENCY
378#define RTT_FREQUENCY (1024U) /* in Hz. */
379#endif
380#endif
383#ifdef __cplusplus
384}
385#endif
386
387#endif /* PERIPH_CPU_COMMON_H */
static atmega_gpio_port_t * atmega_gpio_port(uint8_t port_num)
Get the GPIO PORT registers of the given GPIO PORT.
#define ATMEGA_GPIO_BASE_H
Base of the GPIO registers of the second memory region (port >= H)
#define ATMEGA_GPIO_BASE_A
Base of the GPIO registers as memory address.
@ TIMER_DIV1_8_32_64_128_256_1024
1/{1,8,32,64,128,256,1024}
@ TIMER_DIV1_8_64_128_1024
1/{1,8,64,128,1024}
#define ATMEGA_GPIO_BASE_G
Base of the GPIO port G register as memory address.
gpio_flank_t
Definition periph_cpu.h:180
spi_clk_t
Definition periph_cpu.h:352
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:353
gpio_irq_trig_t
Definition of possible IRQ triggers.
Definition gpio_ll_irq.h:62
@ GPIO_TRIGGER_EDGE_FALLING
edge triggered IRQ on falling flanks only
Definition gpio_ll_irq.h:63
@ GPIO_TRIGGER_LEVEL_HIGH
level triggered IRQ on high input
Definition gpio_ll_irq.h:68
@ GPIO_TRIGGER_EDGE_RISING
edge triggered IRQ on rising flanks only
Definition gpio_ll_irq.h:65
@ GPIO_TRIGGER_EDGE_BOTH
edge triggered IRQ on falling AND rising flanks
Definition gpio_ll_irq.h:66
@ GPIO_TRIGGER_LEVEL_LOW
level triggered IRQ on low input
Definition gpio_ll_irq.h:69
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition gpio_ll.h:243
gpio_state_t
Enumeration of GPIO states (direction)
Definition gpio_ll.h:133
gpio_slew_t
Enumeration of slew rate settings.
Definition gpio_ll.h:307
gpio_drive_strength_t
Enumeration of drive strength options.
Definition gpio_ll.h:274
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition gpio_ll.h:244
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition gpio_ll.h:245
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition gpio_ll.h:246
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition gpio_ll.h:247
@ GPIO_OUTPUT_OPEN_SOURCE
Use pin as output in open emitter configuration.
Definition gpio_ll.h:170
@ GPIO_USED_BY_PERIPHERAL
The GPIO pin is used by a peripheral.
Definition gpio_ll.h:189
@ GPIO_OUTPUT_OPEN_DRAIN
Use pin as output in open collector configuration.
Definition gpio_ll.h:157
@ GPIO_OUTPUT_PUSH_PULL
Use pin as output in push-pull configuration.
Definition gpio_ll.h:144
@ GPIO_DISCONNECT
Disconnect pin from all peripherals.
Definition gpio_ll.h:217
@ GPIO_INPUT
Use pin as input.
Definition gpio_ll.h:176
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition gpio_ll.h:308
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition gpio_ll.h:311
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition gpio_ll.h:310
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition gpio_ll.h:312
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition gpio_ll.h:277
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition gpio_ll.h:276
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition gpio_ll.h:278
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition gpio_ll.h:275
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
Structure describing the memory layout of the registers of a GPIO port on ATmega MCUs.
volatile uint8_t port
Read/write the state of GPIO pins using the Port Data Register.
volatile uint8_t pin
Toggle bits in the port register.
volatile uint8_t ddr
Configure pins as output (1) or input (0) using the Data Direction Register.
8-bit timer register map
PWM device configuration.
timer_div_t div
Timer divider mask.
mini_timer_t * dev
Timer used.