periph_cpu.h

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/*
 * Copyright (C) 2021 Gerson Fernando Budke <nandojve@gmail.com>
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include <avr/io.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CPUID_LEN               (11U)
typedef enum {
    CPU_INT_LVL_OFF,    
    CPU_INT_LVL_LOW,    
    CPU_INT_LVL_MID,    
    CPU_INT_LVL_HIGH,   
} cpu_int_lvl_t;
enum {
    PORT_A,     
    PORT_B,     
    PORT_C,     
    PORT_D,     
    PORT_E,     
    PORT_F,     
    PORT_G,     
    PORT_H,     
    PORT_J,     
    PORT_K,     
    PORT_L,     
    PORT_M,     
    PORT_N,     
    PORT_P,     
    PORT_Q,     
    PORT_R,     
    /* ... */
    PORT_MAX,
};
 
typedef uint16_t pwr_reduction_t;
 
#define PWR_RED_REG(reg, dev) ((reg << 8) | dev)
 
enum {
    PWR_GENERAL_POWER,
    PWR_PORT_A,
    PWR_PORT_B,
    PWR_PORT_C,
    PWR_PORT_D,
    PWR_PORT_E,
    PWR_PORT_F,
};
 
#define PM_NUM_MODES            (5)
#define AVR8_PM_SLEEP_MODE_0    SLEEP_MODE_PWR_DOWN    
#define AVR8_PM_SLEEP_MODE_1    SLEEP_MODE_PWR_SAVE    
#define AVR8_PM_SLEEP_MODE_2    SLEEP_MODE_STANDBY     
#define AVR8_PM_SLEEP_MODE_3    SLEEP_MODE_EXT_STANDBY 
#define GPIO_EXT_INT_NUMOF      (2 * PORT_MAX)
#define HAVE_GPIO_T
typedef uint16_t gpio_t;
#define GPIO_UNDEF              (0xffff)
 
#define ATXMEGA_GPIO_PIN(x, y)  (((x & 0x0f) << 8) | (y & 0xff))
#define GPIO_PIN(x, y)          ATXMEGA_GPIO_PIN(x, (1U << (y & 0x07)))
#define HAVE_GPIO_MODE_T
typedef enum GPIO_MODE {
    GPIO_SLEW_RATE            = (1 << 7), 
    GPIO_INVERTED             = (1 << 6), 
    GPIO_OPC_TOTEN            = (0 << 3), 
    GPIO_OPC_BSKPR            = (1 << 3), 
    GPIO_OPC_PD               = (2 << 3), 
    GPIO_OPC_PU               = (3 << 3), 
    GPIO_OPC_WRD_OR           = (4 << 3), 
    GPIO_OPC_WRD_AND          = (5 << 3), 
    GPIO_OPC_WRD_OR_PULL      = (6 << 3), 
    GPIO_OPC_WRD_AND_PULL     = (7 << 3), 
    GPIO_ANALOG               = (1 << 1), 
    GPIO_IN                   = (0 << 0), 
    GPIO_OUT                  = (1 << 0), 
    /* Compatibility Mode */
    GPIO_IN_PU                = GPIO_IN  | GPIO_OPC_PU,
    GPIO_IN_PD                = GPIO_IN  | GPIO_OPC_PD,
    GPIO_OD                   = GPIO_OUT | GPIO_OPC_WRD_OR,
    GPIO_OD_PU                = GPIO_OUT | GPIO_OPC_WRD_OR_PULL,
} gpio_mode_t;
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_ISC_BOTH             = (0 << 4), 
    GPIO_ISC_RISING           = (1 << 4), 
    GPIO_ISC_FALLING          = (2 << 4), 
    GPIO_ISC_LOW_LEVEL        = (3 << 4), 
    GPIO_INT_DISABLED_ALL     = (1 << 3), 
    GPIO_INT0_VCT             = (0 << 2), 
    GPIO_INT1_VCT             = (1 << 2), 
    GPIO_LVL_OFF              = (0 << 0), 
    GPIO_LVL_LOW              = (1 << 0), 
    GPIO_LVL_MID              = (2 << 0), 
    GPIO_LVL_HIGH             = (3 << 0), 
    /* Compatibility Mode */
    GPIO_FALLING              = GPIO_ISC_FALLING | GPIO_LVL_LOW,
    GPIO_RISING               = GPIO_ISC_RISING  | GPIO_LVL_LOW,
    GPIO_BOTH                 = GPIO_ISC_BOTH    | GPIO_LVL_LOW,
} gpio_flank_t;
#define UART_MAX_NUMOF          (7)
 
#ifndef UART_TXBUF_SIZE
#define UART_TXBUF_SIZE         (64)
#endif
 
typedef struct {
    USART_t *dev;                   
    pwr_reduction_t pwr;            
    gpio_t rx_pin;                  
    gpio_t tx_pin;                  
#ifdef MODULE_PERIPH_UART_HW_FC
    gpio_t rts_pin;                 
    gpio_t cts_pin;                 
#endif
    cpu_int_lvl_t rx_int_lvl;       
    cpu_int_lvl_t tx_int_lvl;       
    cpu_int_lvl_t dre_int_lvl;      
} uart_conf_t;
 
#define TIMER_CH_MAX_NUMOF      (4)
 
#define PERIPH_TIMER_PROVIDES_SET
 
typedef enum {
    TC_TYPE_0                 = 0,
    TC_TYPE_1                 = 1,
    TC_TYPE_2                 = 2,
    TC_TYPE_4                 = 4,
    TC_TYPE_5                 = 5,
} timer_type_t;
 
typedef struct {
    TC0_t *dev;                                 
    pwr_reduction_t pwr;                        
    timer_type_t type;                          
    cpu_int_lvl_t int_lvl[TIMER_CH_MAX_NUMOF];  
} timer_conf_t;
 
#define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW       =   10000ul, 
    I2C_SPEED_NORMAL    =  100000ul, 
    I2C_SPEED_FAST      =  400000ul, 
    I2C_SPEED_FAST_PLUS = 1000000ul, 
    /* High speed is not supported without external hardware hacks */
    I2C_SPEED_HIGH      = 3400000ul, 
} i2c_speed_t;
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_WRITE_REGS
typedef struct {
    TWI_t *dev;             
    pwr_reduction_t pwr;    
    gpio_t sda_pin;         
    gpio_t scl_pin;         
    i2c_speed_t speed;      
    cpu_int_lvl_t int_lvl;  
} i2c_conf_t;
 
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
#define SPI_UNDEF               (UCHAR_MAX)
#define HAVE_SPI_T
typedef uint8_t spi_t;
typedef struct {
    SPI_t *dev;                     
    pwr_reduction_t pwr;            
    gpio_t sck_pin;                 
    gpio_t miso_pin;                
    gpio_t mosi_pin;                
    gpio_t ss_pin;                  
} spi_conf_t;
#define HAVE_SPI_CLK_T
typedef enum {
    SPI_CLK_100KHZ = 100000U,       
    SPI_CLK_400KHZ = 400000U,       
    SPI_CLK_1MHZ   = 1000000U,      
    SPI_CLK_5MHZ   = 5000000U,      
    SPI_CLK_10MHZ  = 10000000U,     
} spi_clk_t;
#if defined(__AVR_ATxmega64A1__)   || \
    defined(__AVR_ATxmega128A1__)  || \
    defined(__AVR_ATxmega64A1U__)  || \
    defined(__AVR_ATxmega128A1U__) || \
    defined(Doxygen)
typedef enum {
    EBI_LPC_MODE_ALE1       = 0x01,     
    EBI_LPC_MODE_ALE12      = 0x03,     
} ebi_lpc_mode_t;
 
typedef enum {
    EBI_PORT_3PORT          = 0x01,     
    EBI_PORT_SDRAM          = 0x02,     
    EBI_PORT_SRAM           = 0x04,     
    EBI_PORT_LPC            = 0x08,     
    EBI_PORT_CS0            = 0x10,     
    EBI_PORT_CS1            = 0x20,     
    EBI_PORT_CS2            = 0x40,     
    EBI_PORT_CS3            = 0x80,     
    EBI_PORT_CS_ALL         = 0xF0,     
} ebi_port_mask_t;
 
typedef enum {
    EBI_SDRAM_CAS_LAT_2CLK  = 0x00,     
    EBI_SDRAM_CAS_LAT_3CLK  = 0x01,     
} ebi_sdram_cas_latency_t;
 
typedef enum {
    EBI_SDRAM_ROW_BITS_11  = 0x00,     
    EBI_SDRAM_ROW_BITS_12  = 0x01,     
} ebi_sdram_row_bits_t;
 
#define PERIPH_EBI_MAX_CS   (4)
 
#define PERIPH_EBI_SDRAM_CS (3)
 
/* for compatibility between different versions of AVR libc: Legacy versions
 * occasionally use ASPACE instead of ASIZE for some MCUs, while new AVR libc
 * uses ASIZE as name consistently */
#ifndef EBI_CS_ASIZE_gm
typedef EBI_CS_ASPACE_t EBI_CS_ASIZE_t;
#define EBI_CS_ASIZE_256B_gc EBI_CS_ASPACE_256B_gc
#define EBI_CS_ASIZE_512B_gc EBI_CS_ASPACE_512B_gc
#define EBI_CS_ASIZE_1KB_gc EBI_CS_ASPACE_1KB_gc
#define EBI_CS_ASIZE_2KB_gc EBI_CS_ASPACE_2KB_gc
#define EBI_CS_ASIZE_4KB_gc EBI_CS_ASPACE_4KB_gc
#define EBI_CS_ASIZE_8KB_gc EBI_CS_ASPACE_8KB_gc
#define EBI_CS_ASIZE_16KB_gc EBI_CS_ASPACE_16KB_gc
#define EBI_CS_ASIZE_32KB_gc EBI_CS_ASPACE_32KB_gc
#define EBI_CS_ASIZE_64KB_gc EBI_CS_ASPACE_64KB_gc
#define EBI_CS_ASIZE_128KB_gc EBI_CS_ASPACE_128KB_gc
#define EBI_CS_ASIZE_256KB_gc EBI_CS_ASPACE_256KB_gc
#define EBI_CS_ASIZE_512KB_gc EBI_CS_ASPACE_512KB_gc
#define EBI_CS_ASIZE_1MB_gc EBI_CS_ASPACE_1MB_gc
#define EBI_CS_ASIZE_2MB_gc EBI_CS_ASPACE_2MB_gc
#define EBI_CS_ASIZE_4MB_gc EBI_CS_ASPACE_4MB_gc
#define EBI_CS_ASIZE_8MB_gc EBI_CS_ASPACE_8MB_gc
#define EBI_CS_ASIZE_16MB_gc EBI_CS_ASPACE_16MB_gc
#endif
 
typedef struct {
    EBI_CS_MODE_t   mode;               
    EBI_CS_ASIZE_t  space;              
    EBI_CS_SRWS_t   wait;               
    uint32_t        address;            
} ebi_cs_t;
 
typedef struct {
    uint8_t refresh;                     
    uint16_t refresh_period;             
    uint16_t init_dly;                   
    EBI_CS_SDMODE_t mode;                
    ebi_sdram_cas_latency_t cas_latency; 
    ebi_sdram_row_bits_t row_bits;       
    EBI_SDCOL_t column_bits;             
    EBI_MRDLY_t ld_mode_dly;             
    EBI_ROWCYCDLY_t row_cycle_dly;       
    EBI_RPDLY_t row_prechage_dly;        
    EBI_WRDLY_t write_recovery_dly;      
    EBI_ESRDLY_t exit_self_rfsh_dly;     
    EBI_ROWCOLDLY_t row_to_column_dly;   
} ebi_sd_t;
 
typedef struct {
    uint8_t addr_bits;                  
    ebi_port_mask_t flags;              
    uint8_t sram_ale;                   
    uint8_t lpc_ale;                    
    ebi_sd_t sdram;                     
    ebi_cs_t cs[PERIPH_EBI_MAX_CS];     
} ebi_conf_t;
#endif /* __AVR_ATxmegaxxxA1x__ */
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */