32#define CPUID_LEN (11U)
79#define PWR_RED_REG(reg, dev) ((reg << 8) | dev)
98#define PM_NUM_MODES (5)
105#define GPIO_EXT_INT_NUMOF (2 * PORT_MAX)
119#define GPIO_UNDEF (0xffff)
131#define ATXMEGA_GPIO_PIN(x, y) (((x & 0x0f) << 8) | (y & 0xff))
132#define GPIO_PIN(x, y) ATXMEGA_GPIO_PIN(x, (1U << (y & 0x07)))
144#define HAVE_GPIO_MODE_T
175#define HAVE_GPIO_FLANK_T
202#define UART_MAX_NUMOF (7)
207#ifndef UART_TXBUF_SIZE
208#define UART_TXBUF_SIZE (64)
219#ifdef MODULE_PERIPH_UART_HW_FC
231#define TIMER_CH_MAX_NUMOF (4)
236#define PERIPH_TIMER_PROVIDES_SET
271#define HAVE_I2C_SPEED_T
286#define PERIPH_I2C_NEED_READ_REG
287#define PERIPH_I2C_NEED_READ_REGS
288#define PERIPH_I2C_NEED_WRITE_REG
289#define PERIPH_I2C_NEED_WRITE_REGS
308#define PERIPH_SPI_NEEDS_INIT_CS
309#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
310#define PERIPH_SPI_NEEDS_TRANSFER_REG
311#define PERIPH_SPI_NEEDS_TRANSFER_REGS
318#define SPI_UNDEF (UCHAR_MAX)
326typedef uint8_t
spi_t;
347#define HAVE_SPI_CLK_T
357#if defined(__AVR_ATxmega64A1__) || \
358 defined(__AVR_ATxmega128A1__) || \
359 defined(__AVR_ATxmega64A1U__) || \
360 defined(__AVR_ATxmega128A1U__) || \
371 EBI_LPC_MODE_ALE1 = 0x01,
372 EBI_LPC_MODE_ALE12 = 0x03,
381 EBI_PORT_3PORT = 0x01,
382 EBI_PORT_SDRAM = 0x02,
383 EBI_PORT_SRAM = 0x04,
389 EBI_PORT_CS_ALL = 0xF0,
396 EBI_SDRAM_CAS_LAT_2CLK = 0x00,
397 EBI_SDRAM_CAS_LAT_3CLK = 0x01,
398} ebi_sdram_cas_latency_t;
404 EBI_SDRAM_ROW_BITS_11 = 0x00,
405 EBI_SDRAM_ROW_BITS_12 = 0x01,
406} ebi_sdram_row_bits_t;
411#define PERIPH_EBI_MAX_CS (4)
416#define PERIPH_EBI_SDRAM_CS (3)
421#ifndef EBI_CS_ASIZE_gm
422typedef EBI_CS_ASPACE_t EBI_CS_ASIZE_t;
423#define EBI_CS_ASIZE_256B_gc EBI_CS_ASPACE_256B_gc
424#define EBI_CS_ASIZE_512B_gc EBI_CS_ASPACE_512B_gc
425#define EBI_CS_ASIZE_1KB_gc EBI_CS_ASPACE_1KB_gc
426#define EBI_CS_ASIZE_2KB_gc EBI_CS_ASPACE_2KB_gc
427#define EBI_CS_ASIZE_4KB_gc EBI_CS_ASPACE_4KB_gc
428#define EBI_CS_ASIZE_8KB_gc EBI_CS_ASPACE_8KB_gc
429#define EBI_CS_ASIZE_16KB_gc EBI_CS_ASPACE_16KB_gc
430#define EBI_CS_ASIZE_32KB_gc EBI_CS_ASPACE_32KB_gc
431#define EBI_CS_ASIZE_64KB_gc EBI_CS_ASPACE_64KB_gc
432#define EBI_CS_ASIZE_128KB_gc EBI_CS_ASPACE_128KB_gc
433#define EBI_CS_ASIZE_256KB_gc EBI_CS_ASPACE_256KB_gc
434#define EBI_CS_ASIZE_512KB_gc EBI_CS_ASPACE_512KB_gc
435#define EBI_CS_ASIZE_1MB_gc EBI_CS_ASPACE_1MB_gc
436#define EBI_CS_ASIZE_2MB_gc EBI_CS_ASPACE_2MB_gc
437#define EBI_CS_ASIZE_4MB_gc EBI_CS_ASPACE_4MB_gc
438#define EBI_CS_ASIZE_8MB_gc EBI_CS_ASPACE_8MB_gc
439#define EBI_CS_ASIZE_16MB_gc EBI_CS_ASPACE_16MB_gc
447 EBI_CS_ASIZE_t space;
457 uint16_t refresh_period;
459 EBI_CS_SDMODE_t mode;
460 ebi_sdram_cas_latency_t cas_latency;
461 ebi_sdram_row_bits_t row_bits;
462 EBI_SDCOL_t column_bits;
463 EBI_MRDLY_t ld_mode_dly;
464 EBI_ROWCYCDLY_t row_cycle_dly;
465 EBI_RPDLY_t row_prechage_dly;
466 EBI_WRDLY_t write_recovery_dly;
467 EBI_ESRDLY_t exit_self_rfsh_dly;
468 EBI_ROWCOLDLY_t row_to_column_dly;
597 ebi_port_mask_t flags;
601 ebi_cs_t cs[PERIPH_EBI_MAX_CS];
#define TIMER_CH_MAX_NUMOF
Max number of available timer channels.
@ GPIO_OUT
select GPIO MASK as output
@ GPIO_IN
select GPIO MASK as input
@ GPIO_OPC_PU
pull-up resistor
@ GPIO_OPC_WRD_AND_PULL
enable wired AND and pull-up resistor
@ GPIO_OPC_TOTEN
select no pull resistor (TOTEM)
@ GPIO_OPC_WRD_AND
enable wired AND
@ GPIO_OPC_WRD_OR_PULL
enable wired OR and pull-down resistor
@ GPIO_OPC_BSKPR
push-pull mode (BUSKEEPER)
@ GPIO_OPC_WRD_OR
enable wired OR
@ GPIO_SLEW_RATE
enable slew rate
@ GPIO_INVERTED
enable inverted signal
@ GPIO_OPC_PD
pull-down resistor
@ GPIO_ANALOG
select GPIO for analog function
uint16_t pwr_reduction_t
Power Reduction Peripheral Mask.
@ CPU_INT_LVL_MID
Interrupt Medium Level.
@ CPU_INT_LVL_OFF
Interrupt Disabled
@ CPU_INT_LVL_LOW
Interrupt Low Level
@ CPU_INT_LVL_HIGH
Interrupt High Level
unsigned int gpio_t
GPIO type identifier.
@ GPIO_FALLING
emit interrupt on falling flank
@ GPIO_ISC_FALLING
emit interrupt on falling flank
@ GPIO_INT0_VCT
enable interrupt on Vector 0 (default)
@ GPIO_INT1_VCT
enable interrupt on Vector 1
@ GPIO_ISC_LOW_LEVEL
emit interrupt on low level
@ GPIO_ISC_BOTH
emit interrupt on both flanks (default)
@ GPIO_RISING
emit interrupt on rising flank
@ GPIO_LVL_LOW
interrupt low level
@ GPIO_BOTH
emit interrupt on both flanks
@ GPIO_INT_DISABLED_ALL
disable all interrupts
@ GPIO_LVL_OFF
interrupt disabled (default)
@ GPIO_LVL_HIGH
interrupt higher
@ GPIO_ISC_RISING
emit interrupt on rising flank
@ GPIO_LVL_MID
interrupt medium level
@ GPIO_OD
configure as output in open-drain mode without pull resistor
@ GPIO_IN_PU
configure as input with pull-up resistor
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
@ GPIO_IN_PD
configure as input with pull-down resistor
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
uint_fast8_t spi_t
Default type for SPI devices.
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
gpio_mode_t
Available pin modes.
I2C configuration structure.
pwr_reduction_t pwr
Power Management.
i2c_speed_t speed
Configured bus speed, actual speed may be lower but never higher.
TWI_t * dev
Pointer to hardware module registers.
cpu_int_lvl_t int_lvl
Serial Interrupt Level.
gpio_t sda_pin
SDA GPIO pin.
gpio_t scl_pin
SCL GPIO pin.
SPI device configuration.
gpio_t miso_pin
pin used for MISO
pwr_reduction_t pwr
Power Management.
gpio_t mosi_pin
pin used for MOSI
gpio_t ss_pin
pin used for SS line
SPI_t * dev
pointer to the used SPI device
gpio_t sck_pin
pin used for SCK
Timer device configuration.
pwr_reduction_t pwr
Power Management.
TC0_t * dev
Pointer to the used as Timer device.
timer_type_t type
Timer Type.
UART device configuration.
USART_t * dev
pointer to the used UART device
cpu_int_lvl_t tx_int_lvl
TX Complete Interrupt Level.
pwr_reduction_t pwr
Power Management.
gpio_t tx_pin
pin used for TX
cpu_int_lvl_t dre_int_lvl
Data Registry Empty Interrupt Level.
gpio_t rx_pin
pin used for RX
cpu_int_lvl_t rx_int_lvl
RX Complete Interrupt Level.