periph_cpu.h
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1/*
2 * Copyright (C) 2021 Gerson Fernando Budke <nandojve@gmail.com>
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CPU_H
20#define PERIPH_CPU_H
21
22#include <avr/io.h>
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
32#define CPUID_LEN (11U)
39typedef enum {
50enum {
67 /* ... */
68 PORT_MAX,
69};
70
74typedef uint16_t pwr_reduction_t;
75
79#define PWR_RED_REG(reg, dev) ((reg << 8) | dev)
80
84enum {
85 PWR_GENERAL_POWER,
86 PWR_PORT_A,
87 PWR_PORT_B,
88 PWR_PORT_C,
89 PWR_PORT_D,
90 PWR_PORT_E,
91 PWR_PORT_F,
92};
93
98#define PM_NUM_MODES (5)
105#define GPIO_EXT_INT_NUMOF (2 * PORT_MAX)
112#define HAVE_GPIO_T
113typedef uint16_t gpio_t;
119#define GPIO_UNDEF (0xffff)
120
131#define ATXMEGA_GPIO_PIN(x, y) (((x & 0x0f) << 8) | (y & 0xff))
132#define GPIO_PIN(x, y) ATXMEGA_GPIO_PIN(x, (1U << (y & 0x07)))
144#define HAVE_GPIO_MODE_T
145typedef enum GPIO_MODE {
146 GPIO_SLEW_RATE = (1 << 7),
147 GPIO_INVERTED = (1 << 6),
149 GPIO_OPC_TOTEN = (0 << 3),
150 GPIO_OPC_BSKPR = (1 << 3),
151 GPIO_OPC_PD = (2 << 3),
152 GPIO_OPC_PU = (3 << 3),
153 GPIO_OPC_WRD_OR = (4 << 3),
154 GPIO_OPC_WRD_AND = (5 << 3),
158 GPIO_ANALOG = (1 << 1),
160 GPIO_IN = (0 << 0),
161 GPIO_OUT = (1 << 0),
163 /* Compatibility Mode */
175#define HAVE_GPIO_FLANK_T
176typedef enum {
177 GPIO_ISC_BOTH = (0 << 4),
178 GPIO_ISC_RISING = (1 << 4),
179 GPIO_ISC_FALLING = (2 << 4),
184 GPIO_INT0_VCT = (0 << 2),
185 GPIO_INT1_VCT = (1 << 2),
187 GPIO_LVL_OFF = (0 << 0),
188 GPIO_LVL_LOW = (1 << 0),
189 GPIO_LVL_MID = (2 << 0),
190 GPIO_LVL_HIGH = (3 << 0),
192 /* Compatibility Mode */
202#define UART_MAX_NUMOF (7)
203
207#ifndef UART_TXBUF_SIZE
208#define UART_TXBUF_SIZE (64)
209#endif
210
214typedef struct {
215 USART_t *dev;
217 gpio_t rx_pin;
218 gpio_t tx_pin;
219#ifdef MODULE_PERIPH_UART_HW_FC
220 gpio_t rts_pin;
221 gpio_t cts_pin;
222#endif
227
231#define TIMER_CH_MAX_NUMOF (4)
232
236#define PERIPH_TIMER_PROVIDES_SET
237
246typedef enum {
247 TC_TYPE_0 = 0,
248 TC_TYPE_1 = 1,
249 TC_TYPE_2 = 2,
250 TC_TYPE_4 = 4,
251 TC_TYPE_5 = 5,
253
260typedef struct {
261 TC0_t *dev;
266
271#define HAVE_I2C_SPEED_T
272typedef enum {
273 I2C_SPEED_LOW = 10000ul,
274 I2C_SPEED_NORMAL = 100000ul,
275 I2C_SPEED_FAST = 400000ul,
277 /* High speed is not supported without external hardware hacks */
278 I2C_SPEED_HIGH = 3400000ul,
286#define PERIPH_I2C_NEED_READ_REG
287#define PERIPH_I2C_NEED_READ_REGS
288#define PERIPH_I2C_NEED_WRITE_REG
289#define PERIPH_I2C_NEED_WRITE_REGS
295typedef struct {
296 TWI_t *dev;
298 gpio_t sda_pin;
299 gpio_t scl_pin;
302} i2c_conf_t;
303
308#define PERIPH_SPI_NEEDS_INIT_CS
309#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
310#define PERIPH_SPI_NEEDS_TRANSFER_REG
311#define PERIPH_SPI_NEEDS_TRANSFER_REGS
318#define SPI_UNDEF (UCHAR_MAX)
325#define HAVE_SPI_T
326typedef uint8_t spi_t;
333typedef struct {
334 SPI_t *dev;
336 gpio_t sck_pin;
337 gpio_t miso_pin;
338 gpio_t mosi_pin;
339 gpio_t ss_pin;
340} spi_conf_t;
347#define HAVE_SPI_CLK_T
348typedef enum {
349 SPI_CLK_100KHZ = 100000U,
350 SPI_CLK_400KHZ = 400000U,
351 SPI_CLK_1MHZ = 1000000U,
352 SPI_CLK_5MHZ = 5000000U,
353 SPI_CLK_10MHZ = 10000000U,
354} spi_clk_t;
357#if defined(__AVR_ATxmega64A1__) || \
358 defined(__AVR_ATxmega128A1__) || \
359 defined(__AVR_ATxmega64A1U__) || \
360 defined(__AVR_ATxmega128A1U__) || \
361 defined(Doxygen)
370typedef enum {
371 EBI_LPC_MODE_ALE1 = 0x01,
372 EBI_LPC_MODE_ALE12 = 0x03,
373} ebi_lpc_mode_t;
374
380typedef enum {
381 EBI_PORT_3PORT = 0x01,
382 EBI_PORT_SDRAM = 0x02,
383 EBI_PORT_SRAM = 0x04,
384 EBI_PORT_LPC = 0x08,
385 EBI_PORT_CS0 = 0x10,
386 EBI_PORT_CS1 = 0x20,
387 EBI_PORT_CS2 = 0x40,
388 EBI_PORT_CS3 = 0x80,
389 EBI_PORT_CS_ALL = 0xF0,
390} ebi_port_mask_t;
391
395typedef enum {
396 EBI_SDRAM_CAS_LAT_2CLK = 0x00,
397 EBI_SDRAM_CAS_LAT_3CLK = 0x01,
398} ebi_sdram_cas_latency_t;
399
403typedef enum {
404 EBI_SDRAM_ROW_BITS_11 = 0x00,
405 EBI_SDRAM_ROW_BITS_12 = 0x01,
406} ebi_sdram_row_bits_t;
407
411#define PERIPH_EBI_MAX_CS (4)
412
416#define PERIPH_EBI_SDRAM_CS (3)
417
418/* for compatibility between different versions of AVR libc: Legacy versions
419 * occasionally use ASPACE instead of ASIZE for some MCUs, while new AVR libc
420 * uses ASIZE as name consistently */
421#ifndef EBI_CS_ASIZE_gm
422typedef EBI_CS_ASPACE_t EBI_CS_ASIZE_t;
423#define EBI_CS_ASIZE_256B_gc EBI_CS_ASPACE_256B_gc
424#define EBI_CS_ASIZE_512B_gc EBI_CS_ASPACE_512B_gc
425#define EBI_CS_ASIZE_1KB_gc EBI_CS_ASPACE_1KB_gc
426#define EBI_CS_ASIZE_2KB_gc EBI_CS_ASPACE_2KB_gc
427#define EBI_CS_ASIZE_4KB_gc EBI_CS_ASPACE_4KB_gc
428#define EBI_CS_ASIZE_8KB_gc EBI_CS_ASPACE_8KB_gc
429#define EBI_CS_ASIZE_16KB_gc EBI_CS_ASPACE_16KB_gc
430#define EBI_CS_ASIZE_32KB_gc EBI_CS_ASPACE_32KB_gc
431#define EBI_CS_ASIZE_64KB_gc EBI_CS_ASPACE_64KB_gc
432#define EBI_CS_ASIZE_128KB_gc EBI_CS_ASPACE_128KB_gc
433#define EBI_CS_ASIZE_256KB_gc EBI_CS_ASPACE_256KB_gc
434#define EBI_CS_ASIZE_512KB_gc EBI_CS_ASPACE_512KB_gc
435#define EBI_CS_ASIZE_1MB_gc EBI_CS_ASPACE_1MB_gc
436#define EBI_CS_ASIZE_2MB_gc EBI_CS_ASPACE_2MB_gc
437#define EBI_CS_ASIZE_4MB_gc EBI_CS_ASPACE_4MB_gc
438#define EBI_CS_ASIZE_8MB_gc EBI_CS_ASPACE_8MB_gc
439#define EBI_CS_ASIZE_16MB_gc EBI_CS_ASPACE_16MB_gc
440#endif
441
445typedef struct {
446 EBI_CS_MODE_t mode;
447 EBI_CS_ASIZE_t space;
448 EBI_CS_SRWS_t wait;
449 uint32_t address;
450} ebi_cs_t;
451
455typedef struct {
456 uint8_t refresh;
457 uint16_t refresh_period;
458 uint16_t init_dly;
459 EBI_CS_SDMODE_t mode;
460 ebi_sdram_cas_latency_t cas_latency;
461 ebi_sdram_row_bits_t row_bits;
462 EBI_SDCOL_t column_bits;
463 EBI_MRDLY_t ld_mode_dly;
464 EBI_ROWCYCDLY_t row_cycle_dly;
465 EBI_RPDLY_t row_prechage_dly;
466 EBI_WRDLY_t write_recovery_dly;
467 EBI_ESRDLY_t exit_self_rfsh_dly;
468 EBI_ROWCOLDLY_t row_to_column_dly;
469} ebi_sd_t;
470
595typedef struct {
596 uint8_t addr_bits;
597 ebi_port_mask_t flags;
598 uint8_t sram_ale;
599 uint8_t lpc_ale;
600 ebi_sd_t sdram;
601 ebi_cs_t cs[PERIPH_EBI_MAX_CS];
602} ebi_conf_t;
605#endif /* __AVR_ATxmegaxxxA1x__ */
606
607#ifdef __cplusplus
608}
609#endif
610
611#endif /* PERIPH_CPU_H */
@ PORT_B
port B
Definition: periph_cpu.h:37
@ PORT_G
port G
Definition: periph_cpu.h:42
@ PORT_C
port C
Definition: periph_cpu.h:38
@ PORT_F
port F
Definition: periph_cpu.h:41
@ PORT_E
port E
Definition: periph_cpu.h:40
@ PORT_A
port A
Definition: periph_cpu.h:36
@ PORT_D
port D
Definition: periph_cpu.h:39
@ PORT_K
port K
Definition: periph_cpu.h:43
@ PORT_H
port H
Definition: periph_cpu.h:41
@ PORT_J
port J
Definition: periph_cpu.h:42
@ PORT_L
port L
Definition: periph_cpu.h:44
#define TIMER_CH_MAX_NUMOF
Max number of available timer channels.
Definition: periph_cpu.h:231
gpio_flank_t
Definition: periph_cpu.h:176
@ PORT_P
port P - 7A0 - D
Definition: periph_cpu.h:64
@ PORT_Q
port Q - 7C0 - E
Definition: periph_cpu.h:65
@ PORT_M
port M - 760 - B
Definition: periph_cpu.h:62
@ PORT_R
port R - 7E0 - F
Definition: periph_cpu.h:66
@ PORT_N
port N - 780 - C
Definition: periph_cpu.h:63
GPIO_MODE
Definition: periph_cpu.h:145
@ GPIO_OUT
select GPIO MASK as output
Definition: periph_cpu.h:161
@ GPIO_IN
select GPIO MASK as input
Definition: periph_cpu.h:160
@ GPIO_OPC_PU
pull-up resistor
Definition: periph_cpu.h:152
@ GPIO_OPC_WRD_AND_PULL
enable wired AND and pull-up resistor
Definition: periph_cpu.h:156
@ GPIO_OPC_TOTEN
select no pull resistor (TOTEM)
Definition: periph_cpu.h:149
@ GPIO_OPC_WRD_AND
enable wired AND
Definition: periph_cpu.h:154
@ GPIO_OPC_WRD_OR_PULL
enable wired OR and pull-down resistor
Definition: periph_cpu.h:155
@ GPIO_OPC_BSKPR
push-pull mode (BUSKEEPER)
Definition: periph_cpu.h:150
@ GPIO_OPC_WRD_OR
enable wired OR
Definition: periph_cpu.h:153
@ GPIO_SLEW_RATE
enable slew rate
Definition: periph_cpu.h:146
@ GPIO_INVERTED
enable inverted signal
Definition: periph_cpu.h:147
@ GPIO_OPC_PD
pull-down resistor
Definition: periph_cpu.h:151
@ GPIO_ANALOG
select GPIO for analog function
Definition: periph_cpu.h:158
timer_type_t
Timer Type.
Definition: periph_cpu.h:246
i2c_speed_t
Definition: periph_cpu.h:272
uint16_t pwr_reduction_t
Power Reduction Peripheral Mask.
Definition: periph_cpu.h:74
cpu_int_lvl_t
Definition: periph_cpu.h:39
@ CPU_INT_LVL_MID
Interrupt Medium Level.
Definition: periph_cpu.h:42
@ CPU_INT_LVL_OFF
Interrupt Disabled
Definition: periph_cpu.h:40
@ CPU_INT_LVL_LOW
Interrupt Low Level
Definition: periph_cpu.h:41
@ CPU_INT_LVL_HIGH
Interrupt High Level
Definition: periph_cpu.h:43
spi_clk_t
Definition: periph_cpu.h:348
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
@ GPIO_FALLING
emit interrupt on falling flank
Definition: periph_cpu.h:93
@ GPIO_ISC_FALLING
emit interrupt on falling flank
Definition: periph_cpu.h:179
@ GPIO_INT0_VCT
enable interrupt on Vector 0 (default)
Definition: periph_cpu.h:184
@ GPIO_INT1_VCT
enable interrupt on Vector 1
Definition: periph_cpu.h:185
@ GPIO_ISC_LOW_LEVEL
emit interrupt on low level
Definition: periph_cpu.h:180
@ GPIO_ISC_BOTH
emit interrupt on both flanks (default)
Definition: periph_cpu.h:177
@ GPIO_RISING
emit interrupt on rising flank
Definition: periph_cpu.h:94
@ GPIO_LVL_LOW
interrupt low level
Definition: periph_cpu.h:188
@ GPIO_BOTH
emit interrupt on both flanks
Definition: periph_cpu.h:95
@ GPIO_INT_DISABLED_ALL
disable all interrupts
Definition: periph_cpu.h:182
@ GPIO_LVL_OFF
interrupt disabled (default)
Definition: periph_cpu.h:187
@ GPIO_LVL_HIGH
interrupt higher
Definition: periph_cpu.h:190
@ GPIO_ISC_RISING
emit interrupt on rising flank
Definition: periph_cpu.h:178
@ GPIO_LVL_MID
interrupt medium level
Definition: periph_cpu.h:189
@ GPIO_OD
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
@ GPIO_IN_PD
configure as input with pull-down resistor
Definition: gpio.h:120
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:274
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition: periph_cpu.h:276
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition: periph_cpu.h:273
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition: periph_cpu.h:278
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: periph_cpu.h:275
uint_fast8_t spi_t
Default type for SPI devices.
Definition: spi.h:119
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition: periph_cpu.h:353
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition: periph_cpu.h:352
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition: periph_cpu.h:350
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition: periph_cpu.h:351
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition: periph_cpu.h:349
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:82
I2C configuration structure.
Definition: periph_cpu.h:295
pwr_reduction_t pwr
Power Management.
Definition: periph_cpu.h:297
i2c_speed_t speed
Configured bus speed, actual speed may be lower but never higher.
Definition: periph_cpu.h:300
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:296
cpu_int_lvl_t int_lvl
Serial Interrupt Level.
Definition: periph_cpu.h:301
gpio_t sda_pin
SDA GPIO pin.
Definition: periph_cpu.h:298
gpio_t scl_pin
SCL GPIO pin.
Definition: periph_cpu.h:299
SPI device configuration.
Definition: periph_cpu.h:333
gpio_t miso_pin
pin used for MISO
Definition: periph_cpu.h:337
pwr_reduction_t pwr
Power Management.
Definition: periph_cpu.h:335
gpio_t mosi_pin
pin used for MOSI
Definition: periph_cpu.h:338
gpio_t ss_pin
pin used for SS line
Definition: periph_cpu.h:339
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:334
gpio_t sck_pin
pin used for SCK
Definition: periph_cpu.h:336
Timer device configuration.
Definition: periph_cpu.h:260
pwr_reduction_t pwr
Power Management.
Definition: periph_cpu.h:262
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:261
timer_type_t type
Timer Type.
Definition: periph_cpu.h:263
UART device configuration.
Definition: periph_cpu.h:214
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:215
cpu_int_lvl_t tx_int_lvl
TX Complete Interrupt Level.
Definition: periph_cpu.h:224
pwr_reduction_t pwr
Power Management.
Definition: periph_cpu.h:216
gpio_t tx_pin
pin used for TX
Definition: periph_cpu.h:218
cpu_int_lvl_t dre_int_lvl
Data Registry Empty Interrupt Level.
Definition: periph_cpu.h:225
gpio_t rx_pin
pin used for RX
Definition: periph_cpu.h:217
cpu_int_lvl_t rx_int_lvl
RX Complete Interrupt Level.
Definition: periph_cpu.h:223