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periph_cpu.h
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1/*
2 * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include <stdbool.h>
19
20#include "periph_cpu_common.h"
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
30#define HAVE_SPI_MODE_T
39typedef enum {
40 SPI_MODE_0 = (UCCKPH),
42 SPI_MODE_2 = (UCCKPL | UCCKPH),
43 SPI_MODE_3 = (UCCKPL)
45
46
51#define HAVE_SPI_CLK_T
55typedef enum {
56 SPI_CLK_100KHZ = 100000,
57 SPI_CLK_400KHZ = 400000,
58 SPI_CLK_1MHZ = 1000000,
59 SPI_CLK_5MHZ = 5000000,
61} spi_clk_t;
62
63
68#define PERIPH_SPI_NEEDS_INIT_CS
69#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
70#define PERIPH_SPI_NEEDS_TRANSFER_REG
71#define PERIPH_SPI_NEEDS_TRANSFER_REGS
73
79typedef enum {
80#ifdef __MSP430_HAS_USCI_AB0__
81 MSP430_USCI_ID_A0,
82 MSP430_USCI_ID_B0,
83#endif
84#ifdef __MSP430_HAS_USCI_AB1__
85 MSP430_USCI_ID_A1,
86 MSP430_USCI_ID_B1,
87#endif
90
105
114
118typedef struct {
120 uint8_t br0;
121 uint8_t br1;
122 uint8_t mctl;
124
135
150
154typedef struct {
157
174
178typedef struct {
180} spi_conf_t;
181
186
191
210 const msp430_usci_conf_t *conf);
211
218
232
237
242
247
252
257
262
263#ifdef __cplusplus
264}
265#endif
266
#define REG8
Register types.
spi_clk_t
Definition periph_cpu.h:348
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:353
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:352
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:350
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:351
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:349
#define UCSSEL_ACLK
Clock USCI using auxiliary clock.
#define UCSSEL_SMCLK
Clock USCI using sub-system master clock.
#define UCSSEL_UCLKI
Clock USCI using CLKI (n/a in SPI mode)
msp430_port_p7_p8_t PORT_8
Register map of GPIO PORT 8.
const msp430_usci_spi_params_t usci_b1_as_spi
MSP430 F2xx/G2xx USCI B1 in SPI configuration.
void msp430_usci_acquire(const msp430_usci_params_t *params, const msp430_usci_conf_t *conf)
Acquire and initialize USCI for use a SPI/UART peripheral.
void msp430_usci_release(const msp430_usci_params_t *params)
Release an USCI, so that it can be used to provide other peripherals.
const msp430_usci_spi_params_t usci_a1_as_spi
MSP430 F2xx/G2xx USCI A1 in SPI configuration.
msp430_port_p7_p8_t PORT_7
Register map of GPIO PORT 7.
const msp430_usci_spi_params_t usci_b0_as_spi
MSP430 F2xx/G2xx USCI B0 in SPI configuration.
const msp430_usci_uart_params_t usci_a1_as_uart
MSP430 F2xx/G2xx USCI A1 in UART configuration.
msp430_usci_clk_t
MSP430 F2xx/G2xx USCI clock source.
Definition periph_cpu.h:109
@ USCI_CLK_SUBMAIN
sub-system master clock source
Definition periph_cpu.h:112
@ USCI_CLK_AUX
auxiliary clock source
Definition periph_cpu.h:111
@ USCI_CLK_UCLKI
UCLKI clock source (not supported yet)
Definition periph_cpu.h:110
const msp430_usci_spi_params_t usci_a0_as_spi
MSP430 F2xx/G2xx USCI A0 in SPI configuration.
const msp430_usci_uart_params_t usci_a0_as_uart
MSP430 F2xx/G2xx USCI A0 in UART configuration.
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:39
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:40
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:42
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:41
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:43
msp430_usci_prescaler_t msp430_usci_prescale(uint32_t target_hz)
Calculate prescaler settings for the given target frequency.
msp430_usci_id_t
Identifiers for USCI instances.
Definition periph_cpu.h:79
@ MSP430_USCI_ID_NUMOF
Number of USCI IDs (also: number of USCI instances)
Definition periph_cpu.h:88
GPIO Port 7/8 (different register layout than Ports 1-6)
Definition msp430_regs.h:71
Universal Serial Control Interface Type B (USCI_B) Registers.
MSP430 F2xx/G2xx USCI configuration registers.
Definition periph_cpu.h:131
uint8_t ctl0
USCI control register 0.
Definition periph_cpu.h:133
msp430_usci_prescaler_t prescaler
Prescaler configuration.
Definition periph_cpu.h:132
MSP430 F2xx/G2xx USCI configuration.
Definition periph_cpu.h:96
REG8 * interrupt_enable
The interrupt enable register matching the USCI.
Definition periph_cpu.h:99
msp430_usci_b_t * dev
The USCI device to use.
Definition periph_cpu.h:97
REG8 * interrupt_flag
The interrupt flag register matching the USCI.
Definition periph_cpu.h:100
uint8_t rx_irq_mask
The bitmask to enable the TX IRQ for this USCI.
Definition periph_cpu.h:102
msp430_usci_id_t id
ID of the USCI.
Definition periph_cpu.h:103
uint8_t tx_irq_mask
The bitmask to enable the TX IRQ for this USCI.
Definition periph_cpu.h:101
MSP430 F2xx/G2xx USCI prescaler configuration.
Definition periph_cpu.h:118
uint8_t br0
What to write in the BR0 register.
Definition periph_cpu.h:120
msp430_usci_clk_t clk_source
Clock source to use.
Definition periph_cpu.h:119
uint8_t br1
What to write in the BR1 register.
Definition periph_cpu.h:121
uint8_t mctl
USCI modulation control register.
Definition periph_cpu.h:122
MSP430 F2xx/G2xx SPI configuration, CPU level.
Definition periph_cpu.h:168
gpio_t mosi
COPI (MOSI) pin.
Definition periph_cpu.h:171
gpio_t miso
CIPO (MISO) pin.
Definition periph_cpu.h:170
msp430_usci_params_t usci_params
The USCI parameters.
Definition periph_cpu.h:169
MSP430 F2xx/G2xx UART configuration, CPU level.
Definition periph_cpu.h:145
msp430_usci_params_t usci_params
The USCI params.
Definition periph_cpu.h:146
SPI device configuration.
Definition periph_cpu.h:333
const msp430_usci_spi_params_t * spi
The SPI configuration to use.
Definition periph_cpu.h:179
UART device configuration.
Definition periph_cpu.h:214
const msp430_usci_uart_params_t * uart
The UART configuration to use.
Definition periph_cpu.h:155