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msp430_regs.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
21
22#include <stdint.h>
23#include <stddef.h>
24
25#include "msp430_regs_common.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
40#define MSP430_USCI_A_B_OFFSET 3U
41
53#define MSP430_USCI_B_FROM_USCI_A(usci_a) \
54 ((msp430_usci_b_t *)((uintptr_t)(usci_a) + MSP430_USCI_A_B_OFFSET))
55
67
71typedef struct {
73 uint8_t _padding1;
75 uint8_t _padding2;
77 uint8_t _padding3;
80
97
111
120#define UCSSEL_UCLKI UCSSEL_0
121#define UCSSEL_ACLK UCSSEL_1
122#define UCSSEL_SMCLK UCSSEL_2
123
124#if (UCSSEL0 == 0x40) || DOXYGEN
125# define UCSSEL_Pos 6
126#else
127# error "USSEL field in USCI CTL1 register is at unexpected position"
128#endif
130
139#define UCBRS_MASK UCBRS_7
141#if (UCBRS_7 == 0x0E) || defined(DOXYGEN)
142# define UCBRS_Pos 1
144#else
145/* The datasheet for the whole MCU family states the field is in bits 3-1,
146 * but let's better be safe than sorry here */
147# error "UCBRS field in the UCAxMCTL register at unexpected position."
148#endif
149
151
167{
168 uintptr_t usci_b = (uintptr_t)usci_a + offsetof(msp430_usci_a_t, CTL0);
169 return (msp430_usci_b_t *)usci_b;
170}
171
201
202#ifdef __cplusplus
203}
204#endif
205
#define REG8
Register types.
msp430_usci_a_t USCI_A0
USCI_A0 register map.
msp430_usci_b_t USCI_B1
USCI_B1 register map.
msp430_usci_b_t USCI_B0
USCI_B0 register map.
static msp430_usci_b_t * msp430_usci_b_from_usci_a(msp430_usci_a_t *usci_a)
"Convert" a USCI A into an USCI B interface
msp430_usci_a_t USCI_A1
USCI_A1 register map.
Cortex CMSIS style definition of MSP430 registers.
GPIO Port 1/2 (with interrupt functionality)
Definition msp430_regs.h:59
REG8 IFG
interrupt flag
Definition msp430_regs.h:61
REG8 SEL
alternative function select
Definition msp430_regs.h:64
REG8 IES
interrupt edge select
Definition msp430_regs.h:62
REG8 REN
pull resistor enable
Definition msp430_regs.h:65
msp430_port_t base
common GPIO port registers
Definition msp430_regs.h:60
REG8 IE
interrupt enable
Definition msp430_regs.h:63
GPIO Port 7/8 (different register layout than Ports 1-6)
Definition msp430_regs.h:71
REG8 IN
input data
Definition msp430_regs.h:72
uint8_t _padding1
unrelated I/O
Definition msp430_regs.h:73
REG8 OD
output data
Definition msp430_regs.h:74
uint8_t _padding3
unrelated I/O
Definition msp430_regs.h:77
REG8 SEL
alternative function select
Definition msp430_regs.h:78
REG8 DIR
pin direction
Definition msp430_regs.h:76
uint8_t _padding2
unrelated I/O
Definition msp430_regs.h:75
Common MSP GPIO Port Registers.
Universal Serial Control Interface Type A (USCI_A) Registers.
Definition msp430_regs.h:84
REG8 MCTL
modulation control
Definition msp430_regs.h:92
REG8 IRTCTL
IrDA transmit control.
Definition msp430_regs.h:86
REG8 TXBUF
transmit buffer
Definition msp430_regs.h:95
REG8 ABCTL
auto baud rate control
Definition msp430_regs.h:85
REG8 BR1
baud rate control 1
Definition msp430_regs.h:91
REG8 BR0
baud rate control 0
Definition msp430_regs.h:90
REG8 STAT
status register
Definition msp430_regs.h:93
REG8 RXBUF
receive buffer
Definition msp430_regs.h:94
REG8 CTL1
control 1
Definition msp430_regs.h:89
REG8 IRRCTL
IrDA receive control.
Definition msp430_regs.h:87
REG8 CTL0
control 0
Definition msp430_regs.h:88
Universal Serial Control Interface Type B (USCI_B) Registers.
REG8 RXBUF
receive buffer
REG8 BR1
baud rate control 1
REG8 BR0
baud rate control 0
REG8 STAT
status register
REG8 CTL1
control 1
REG8 CTL0
control 0
REG8 TXBUF
transmit buffer
REG8 MCTL
modulation control