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periph_cpu_common.h
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1/*
2 * SPDX-FileCopyrightText: 2015-2018 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "cpu.h"
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
27#ifdef NRF_FICR_S
28#define NRF_FICR NRF_FICR_S
29#endif
30
35#ifdef CPU_MODEL_NRF52832XXAA
36#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
37#endif
38
43#define PROVIDES_PM_OFF
45
49#ifdef FICR_INFO_DEVICEID_DEVICEID_Msk
50#define CPUID_ADDR (&NRF_FICR->INFO.DEVICEID[0])
51#else
52#define CPUID_ADDR (&NRF_FICR->DEVICEID[0])
53#endif
57#define CPUID_LEN (8U)
58
64#if GPIO_COUNT > 1
65#define GPIO_PIN(x, y) ((x << 5) | y)
66#else
67#define GPIO_PIN(x, y) ((x & 0) | y)
68#endif
69
73/* The precise value matters where GPIO_UNDEF is set in registers like
74 * PWM.PSEL.OUT where it is used in sign-extended form to get a UINT32_MAX */
75#define GPIO_UNDEF (UINT8_MAX)
76
83#ifdef NRF_GPIOTE0_S
84#define ISR_GPIOTE isr_gpiote0
85#else
86#define ISR_GPIOTE isr_gpiote
87#endif
88
98#define GPIO_MODE(oe, ic, pr, dr) (oe | (ic << 1) | (pr << 2) | (dr << 8))
99
100#ifndef DOXYGEN /* BEGIN: GPIO LL overwrites */
101#define HAVE_GPIO_SLEW_T
102typedef enum {
104 GPIO_SLEW_SLOW = 0,
105 GPIO_SLEW_FAST = 0,
108
109#define HAVE_GPIO_PULL_STRENGTH_T
110typedef enum {
112 GPIO_PULL_WEAK = 0,
116
117#define HAVE_GPIO_DRIVE_STRENGTH_T
118typedef enum {
120 GPIO_DRIVE_WEAK = 0,
124
125#define HAVE_GPIO_IRQ_TRIG_T
126typedef enum {
127 GPIO_TRIGGER_EDGE_RISING = GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos,
128 GPIO_TRIGGER_EDGE_FALLING = GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos,
133
134#define HAVE_GPIO_PULL_T
135typedef enum {
136 GPIO_FLOATING = 0,
137 GPIO_PULL_UP = GPIO_PIN_CNF_PULL_Pullup,
138 GPIO_PULL_DOWN = GPIO_PIN_CNF_PULL_Pulldown,
139 GPIO_PULL_KEEP = 2,
141
142#define HAVE_GPIO_STATE_T
143typedef enum {
151
152#define HAVE_GPIO_CONF_T
153typedef union gpio_conf_nrf5x gpio_conf_t;
154
155#endif
156
162 uint8_t bits;
163 struct {
196 uint8_t : 1;
197 };
198};
199/* END: GPIO LL overwrites */
200
201#if !defined(DOXYGEN) && (defined(CPU_NRF53) || defined(CPU_NRF9160))
205#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
206#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
207#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
208#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
209#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
210#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
211#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
212#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
213#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
214#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
215#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
216#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
217#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
218#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
219#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
220#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
221#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
222#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
223
224#define SPI_FREQUENCY_FREQUENCY_K125 SPIM_FREQUENCY_FREQUENCY_K125
225#define SPI_FREQUENCY_FREQUENCY_K500 SPIM_FREQUENCY_FREQUENCY_K500
226#define SPI_FREQUENCY_FREQUENCY_M1 SPIM_FREQUENCY_FREQUENCY_M1
227#define SPI_FREQUENCY_FREQUENCY_M4 SPIM_FREQUENCY_FREQUENCY_M4
228#define SPI_FREQUENCY_FREQUENCY_M8 SPIM_FREQUENCY_FREQUENCY_M8
229#define SPI_CONFIG_CPHA_Msk SPIM_CONFIG_CPHA_Msk
230#define SPI_CONFIG_CPOL_Msk SPIM_CONFIG_CPOL_Msk
231#endif
232
236#define SPI_HWCS(x) (SPI_CS_UNDEF)
237
242#define PERIPH_SPI_NEEDS_INIT_CS
243#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
244#define PERIPH_SPI_NEEDS_TRANSFER_REG
245#define PERIPH_SPI_NEEDS_TRANSFER_REGS
247
248#ifndef DOXYGEN
253#define HAVE_GPIO_T
254typedef uint8_t gpio_t;
256
266#define HAVE_GPIO_MODE_T
267typedef enum {
268 GPIO_IN = GPIO_MODE(0, 0, 0, 0),
269 GPIO_IN_PD = GPIO_MODE(0, 0, 1, 0),
270 GPIO_IN_PU = GPIO_MODE(0, 0, 3, 0),
271 GPIO_IN_OD_PU = GPIO_MODE(0, 0, 3, 6),
272 GPIO_OUT = GPIO_MODE(1, 1, 0, 0),
273 GPIO_OD = (0xff),
274 GPIO_OD_PU = (0xfe)
277
282#define HAVE_GPIO_FLANK_T
283typedef enum {
284 GPIO_FALLING = 2,
285 GPIO_RISING = 1,
286 GPIO_BOTH = 3
289#endif /* ndef DOXYGEN */
290
294typedef struct {
295 NRF_TIMER_Type *dev;
303 uint8_t channels;
304 uint8_t bitmode;
305 uint8_t irqn;
307
311#define PERIPH_TIMER_PROVIDES_SET 1
312
321#define TIMER_CHANNEL_NUMOF 5
322
323#ifndef DOXYGEN
328#define HAVE_SPI_MODE_T
329typedef enum {
330 SPI_MODE_0 = 0,
331 SPI_MODE_1 = SPI_CONFIG_CPHA_Msk,
332 SPI_MODE_2 = SPI_CONFIG_CPOL_Msk,
333 SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)
334} spi_mode_t;
336
341#define HAVE_SPI_CLK_T
342typedef enum {
343 SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125,
344 SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500,
345 SPI_CLK_1MHZ = SPI_FREQUENCY_FREQUENCY_M1,
346 SPI_CLK_5MHZ = SPI_FREQUENCY_FREQUENCY_M4,
347 SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8
348} spi_clk_t;
350#endif /* ndef DOXYGEN */
351
356#define NWDT_TIME_LOWER_LIMIT (1)
357/* Set upper limit to the maximum possible value that could go in CRV register */
358#define NWDT_TIME_UPPER_LIMIT ((UINT32_MAX >> 15) * US_PER_MS + 1)
360
364typedef struct {
365 gpio_t a_pin;
366 gpio_t b_pin;
367 gpio_t led_pin;
371
380uint8_t gpio_int_get_exti(gpio_t pin);
381
385typedef struct {
386#ifdef UARTE_PRESENT
387 NRF_UARTE_Type *dev;
389#else
390 NRF_UART_Type *dev;
391#endif
392 gpio_t rx_pin;
393 gpio_t tx_pin;
394#ifdef MODULE_PERIPH_UART_HW_FC
395 gpio_t rts_pin;
396 gpio_t cts_pin;
397#endif
398 uint8_t irqn;
400
404#ifndef UART_TXBUF_SIZE
405#define UART_TXBUF_SIZE (64)
406#endif
407
411#define USBDEV_CPU_DMA_ALIGNMENT (4)
412
416#define USBDEV_CPU_DMA_REQUIREMENTS __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
417
418#if !defined(CPU_FAM_NRF51) && !defined(DOXYGEN)
423#define PWM_CHANNELS (4U)
424
432#define PWM_MODE(ud, pol) (ud | (pol << 15))
433
437#define HAVE_PWM_MODE_T
438typedef enum {
439 PWM_LEFT = PWM_MODE(0, 1),
440 PWM_RIGHT = PWM_MODE(0, 0),
441 PWM_CENTER = PWM_MODE(1, 1),
442 PWM_CENTER_INV = PWM_MODE(1, 0)
443} pwm_mode_t;
444
459#if defined(PWM_PRESENT)
460typedef struct {
461 NRF_PWM_Type *dev;
462 gpio_t pin[PWM_CHANNELS];
463} pwm_conf_t;
464#endif
465#endif /* ndef CPU_FAM_NRF51 */
466#ifndef CPU_NRF51
467
471#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
472#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)
473#define SPI_MISOSEL (dev(bus)->PSEL.MISO)
474
478typedef struct {
479 NRF_SPIM_Type *dev;
480 gpio_t sclk;
481 gpio_t mosi;
482 gpio_t miso;
483#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
484 uint8_t ppi;
485#endif
486} spi_conf_t;
487
493typedef void (*shared_irq_cb_t)(void *arg);
494
502void shared_irq_register_spi(NRF_SPIM_Type *bus,
503 shared_irq_cb_t cb, void *arg);
504
512void shared_irq_register_i2c(NRF_TWIM_Type *bus,
513 shared_irq_cb_t cb, void *arg);
514
522void shared_irq_register_uart(NRF_UARTE_Type *bus,
523 shared_irq_cb_t cb, void *arg);
524
532void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg);
533
539void nrf5x_i2c_release(NRF_TWIM_Type *bus);
540
548void nrf5x_spi_acquire(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg);
549
555void nrf5x_spi_release(NRF_SPIM_Type *bus);
556
560#ifndef UART_TXBUF_SIZE
561#define UART_TXBUF_SIZE (64)
562#endif
563
568#ifndef CONFIG_SPI_MBUF_SIZE
569#define CONFIG_SPI_MBUF_SIZE 64
570#endif
571
572#ifndef DOXYGEN
577#define HAVE_I2C_SPEED_T
578typedef enum {
579 I2C_SPEED_LOW = 0xff,
580 I2C_SPEED_NORMAL = TWIM_FREQUENCY_FREQUENCY_K100,
581 I2C_SPEED_FAST = TWIM_FREQUENCY_FREQUENCY_K400,
582 I2C_SPEED_FAST_PLUS = 0xfe,
583 I2C_SPEED_HIGH = 0xfd,
586#endif /* ndef DOXYGEN */
587
592typedef struct {
593 NRF_TWIM_Type *dev;
594 gpio_t scl;
595 gpio_t sda;
597} i2c_conf_t;
599
604#define PERIPH_I2C_NEED_READ_REG
605#define PERIPH_I2C_NEED_WRITE_REG
607
612#define i2c_pin_sda(dev) i2c_config[dev].sda
613#define i2c_pin_scl(dev) i2c_config[dev].scl
615#endif /* ndef CPU_NRF51 */
616
617#ifdef __cplusplus
618}
619#endif
620
gpio_flank_t
Definition periph_cpu.h:176
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:161
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:160
i2c_speed_t
Definition periph_cpu.h:272
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition periph_cpu.h:276
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition periph_cpu.h:273
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition periph_cpu.h:278
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:275
spi_clk_t
Definition periph_cpu.h:348
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:353
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:352
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:350
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:351
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:349
pwm_mode_t
@ PWM_CENTER
center aligned
@ PWM_LEFT
left aligned
@ PWM_RIGHT
right aligned
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:88
gpio_irq_trig_t
Definition of possible IRQ triggers.
Definition gpio_ll_irq.h:71
@ GPIO_TRIGGER_EDGE_FALLING
edge triggered IRQ on falling flanks only
Definition gpio_ll_irq.h:72
@ GPIO_TRIGGER_LEVEL_HIGH
level triggered IRQ on high input
Definition gpio_ll_irq.h:77
@ GPIO_TRIGGER_EDGE_RISING
edge triggered IRQ on rising flanks only
Definition gpio_ll_irq.h:74
@ GPIO_TRIGGER_EDGE_BOTH
edge triggered IRQ on falling AND rising flanks
Definition gpio_ll_irq.h:75
@ GPIO_TRIGGER_LEVEL_LOW
level triggered IRQ on low input
Definition gpio_ll_irq.h:78
gpio_pull_t
Enumeration of pull resistor configurations.
Definition gpio_ll.h:257
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition gpio_ll.h:275
gpio_state_t
Enumeration of GPIO states (direction)
Definition gpio_ll.h:165
gpio_slew_t
Enumeration of slew rate settings.
Definition gpio_ll.h:339
gpio_drive_strength_t
Enumeration of drive strength options.
Definition gpio_ll.h:306
typedef gpio_conf_t
GPIO pin configuration.
Definition gpio_ll.h:423
@ GPIO_FLOATING
No pull ups nor pull downs enabled.
Definition gpio_ll.h:258
@ GPIO_PULL_KEEP
Keep the signal at current logic level with pull up/down resistors.
Definition gpio_ll.h:261
@ GPIO_PULL_DOWN
Pull down resistor enabled.
Definition gpio_ll.h:260
@ GPIO_PULL_UP
Pull up resistor enabled.
Definition gpio_ll.h:259
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition gpio_ll.h:276
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition gpio_ll.h:277
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition gpio_ll.h:278
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition gpio_ll.h:279
@ GPIO_OUTPUT_OPEN_SOURCE
Use pin as output in open emitter configuration.
Definition gpio_ll.h:202
@ GPIO_USED_BY_PERIPHERAL
The GPIO pin is used by a peripheral.
Definition gpio_ll.h:221
@ GPIO_OUTPUT_OPEN_DRAIN
Use pin as output in open collector configuration.
Definition gpio_ll.h:189
@ GPIO_OUTPUT_PUSH_PULL
Use pin as output in push-pull configuration.
Definition gpio_ll.h:176
@ GPIO_DISCONNECT
Disconnect pin from all peripherals.
Definition gpio_ll.h:249
@ GPIO_INPUT
Use pin as input.
Definition gpio_ll.h:208
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition gpio_ll.h:340
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition gpio_ll.h:343
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition gpio_ll.h:342
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition gpio_ll.h:344
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition gpio_ll.h:309
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition gpio_ll.h:308
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition gpio_ll.h:310
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition gpio_ll.h:307
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:39
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:40
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:42
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:41
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:43
void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg)
Acquire the shared I2C/SPI peripheral in I2C mode.
uint8_t gpio_int_get_exti(gpio_t pin)
Retrieve the exti(GPIOTE) channel associated with a gpio.
void shared_irq_register_i2c(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg)
Register an I2C IRQ handler for a shared UART/I2C/SPI irq vector.
void nrf5x_spi_release(NRF_SPIM_Type *bus)
Acquire the shared I2C/SPI peripheral in SPI mode.
void(* shared_irq_cb_t)(void *arg)
Common UART/SPI/I2C interrupt callback.
#define GPIO_MODE(oe, ic, pr, dr)
Generate GPIO mode bitfields.
void nrf5x_spi_acquire(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg)
Acquire the shared I2C/SPI peripheral in SPI mode.
void shared_irq_register_spi(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg)
Register a SPI IRQ handler for a shared UART/I2C/SPI irq vector.
void shared_irq_register_uart(NRF_UARTE_Type *bus, shared_irq_cb_t cb, void *arg)
Register an UART IRQ handler for a shared UART/I2C/SPI irq vector.
void nrf5x_i2c_release(NRF_TWIM_Type *bus)
Release the shared I2C/SPI peripheral in I2C mode.
I2C configuration structure.
Definition periph_cpu.h:295
i2c_speed_t speed
Configured bus speed, actual speed may be lower but never higher.
Definition periph_cpu.h:300
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:296
gpio_t sda
GPIO used as SDA pin.
Definition periph_cpu.h:468
gpio_t scl
GPIO used as SCL pin.
Definition periph_cpu.h:467
PWM device configuration.
Quadrature decoder configuration struct.
bool debounce_filter
Enable/disable debounce filter.
gpio_t b_pin
GPIO Pin for phase B.
gpio_t a_pin
GPIO Pin for phase A.
gpio_t led_pin
LED GPIO, GPIO_UNDEF to disable.
uint8_t sample_period
Sample period used, e.g.
SPI device configuration.
Definition periph_cpu.h:333
gpio_t mosi
GPIO used as MOSI pin.
Definition periph_cpu.h:863
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:334
gpio_t sclk
SCLK pin.
Definition periph_cpu.h:86
gpio_t miso
GPIO used as MISO pin.
Definition periph_cpu.h:864
Timer device configuration.
Definition periph_cpu.h:260
uint8_t irqn
global IRQ channel
Definition periph_cpu.h:320
uint8_t bitmode
counter width
int channels
Number of channels for the timer.
Definition periph_cpu.h:113
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:261
UART device configuration.
Definition periph_cpu.h:214
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:215
uint8_t irqn
IRQ channel.
Definition periph_cpu.h:332
gpio_t tx_pin
pin used for TX
Definition periph_cpu.h:218
gpio_t rx_pin
pin used for RX
Definition periph_cpu.h:217
GPIO pin configuration for nRF5x MCUs.
gpio_pull_t pull
Pull resistor configuration.
gpio_drive_strength_t drive_strength
Drive strength of the GPIO.
gpio_state_t state
State of the pin.
bool initial_value
Initial value of the output.
uint8_t bits
the raw bits