periph_cpu.h

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/*
 * Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
 *               2023 Gunar Schorcht <gunar@schorcht.net>
 *
 * This file is subject to the terms and conditions of the GNU Lesser General
 * Public License v2.1. See the file LICENSE in the top level directory for more
 * details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include <inttypes.h>
 
#include "cpu.h"
#include "clic.h"
#include "kernel_defines.h"
#include "macros/units.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define PM_NUM_MODES    (3U)    
enum {
    GD32V_PM_STANDBY = 0,       
    GD32V_PM_DEEPSLEEP = 1,     
    GD32V_PM_IDLE = 2           
};
 
#ifndef CONFIG_PM_EWUP_USED
#define CONFIG_PM_EWUP_USED     (0U)
#endif
typedef enum {
    AHB,    
    APB1,   
    APB2,   
} bus_t;
 
enum {
#ifdef GPIOA
    PORT_A  = 0,            
#endif
#ifdef GPIOB
    PORT_B  = 1,            
#endif
#ifdef GPIOC
    PORT_C  = 2,            
#endif
#ifdef GPIOD
    PORT_D  = 3,            
#endif
#ifdef GPIOE
    PORT_E  = 4,            
#endif
};
 
#ifndef DOXYGEN
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
#define GPIO_UNDEF          (0xffffffff)
 
#define GPIO_PIN(x, y)      ((GPIOA_BASE + (x << 10)) | y)
 
#define GPIO_MODE(io, pr, ot)   ((io << 0) | (pr << 2) | (ot << 4))
 
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN     = GPIO_MODE(0, 1, 0),   
    GPIO_IN_PD  = GPIO_MODE(0, 2, 0),   
    GPIO_IN_PU  = GPIO_MODE(0, 2, 1),   
    GPIO_OUT    = GPIO_MODE(3, 0, 0),   
    GPIO_OD     = GPIO_MODE(3, 1, 0),   
    GPIO_OD_PU  = (0xff)                
} gpio_mode_t;
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_RISING = 1,        
    GPIO_FALLING = 2,       
    GPIO_BOTH = 3           
} gpio_flank_t;
#endif /* ndef DOXYGEN */
 
typedef enum {
    GPIO_AF_OUT_PP  = 0xb,  
    GPIO_AF_OUT_OD  = 0xf,  
} gpio_af_t;
 
void gpio_init_af(gpio_t pin, gpio_af_t af);
 
void gpio_init_analog(gpio_t pin);
 
/* Hide this from Doxygen to avoid merging implementation details into
 * public view on type */
#ifndef DOXYGEN
 
#define HAVE_GPIO_PULL_STRENGTH_T
typedef enum {
    GPIO_PULL_WEAKEST = 0,
    GPIO_PULL_WEAK = 0,
    GPIO_PULL_STRONG = 0,
    GPIO_PULL_STRONGEST = 0
} gpio_pull_strength_t;
 
#define HAVE_GPIO_DRIVE_STRENGTH_T
typedef enum {
    GPIO_DRIVE_WEAKEST = 0,
    GPIO_DRIVE_WEAK = 0,
    GPIO_DRIVE_STRONG = 0,
    GPIO_DRIVE_STRONGEST = 0
} gpio_drive_strength_t;
 
#define HAVE_GPIO_SLEW_T
typedef enum {
    GPIO_SLEW_SLOWEST = 0,
    GPIO_SLEW_SLOW = 1,
    GPIO_SLEW_FAST = 2,
    GPIO_SLEW_FASTEST = 2,
} gpio_slew_t;
 
#endif /* !DOXYGEN */
 
#define ADC_DEVS            (2U)
 
typedef struct {
    gpio_t pin;             
    uint8_t dev;            
    uint8_t chan;           
} adc_conf_t;
 
#define DAC_CHANNEL_NUMOF (2)
 
typedef struct {
    gpio_t pin;             
    uint8_t chan;           
} dac_conf_t;
 
#define TIMER_CHANNEL_NUMOF (4U)
 
#define TIMER_CHANNEL(tim, chan) *(&dev(tim)->CH0CV + (chan * 2))
 
typedef struct {
    TIMER_Type *dev;        
    uint32_t max;           
    uint32_t rcu_mask;      
    uint8_t bus;            
    uint8_t irqn;           
} timer_conf_t;
 
typedef struct {
    USART_Type *dev;        
    uint32_t rcu_mask;      
    gpio_t rx_pin;          
    gpio_t tx_pin;          
    uint8_t bus;            
    uint8_t irqn;           
} uart_conf_t;
 
#define UART_ISR_PRIO       (2)
 
#define SPI_HWCS_MASK       (0xffffff00)
 
#define SPI_HWCS(x)         (SPI_HWCS_MASK | x)
 
#define SPI_CS_UNDEF        (GPIO_UNDEF)
 
#ifndef DOXYGEN
#define HAVE_SPI_CS_T
typedef uint32_t spi_cs_t;
#endif
 
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
#define HAVE_SPI_CLK_T
enum {
    SPI_CLK_100KHZ = KHZ(100), 
    SPI_CLK_400KHZ = KHZ(400), 
    SPI_CLK_1MHZ   = MHZ(1),   
    SPI_CLK_5MHZ   = MHZ(5),   
    SPI_CLK_10MHZ  = MHZ(10),  
};
 
typedef uint32_t spi_clk_t;
typedef struct {
    SPI_Type *dev;          
    gpio_t mosi_pin;        
    gpio_t miso_pin;        
    gpio_t sclk_pin;        
    spi_cs_t cs_pin;        
    uint32_t rcumask;       
    uint8_t apbbus;         
#ifdef MODULE_PERIPH_DMA
    dma_t tx_dma;           
    uint8_t tx_dma_chan;    
    dma_t rx_dma;           
    uint8_t rx_dma_chan;    
#endif
} spi_conf_t;
 
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REGS
#ifndef DOXYGEN
#define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW       = KHZ(10),      
    I2C_SPEED_NORMAL    = KHZ(100),     
    I2C_SPEED_FAST      = KHZ(400),     
    I2C_SPEED_FAST_PLUS = MHZ(1),       
} i2c_speed_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    I2C_Type *dev;              
    i2c_speed_t speed;          
    gpio_t scl_pin;             
    gpio_t sda_pin;             
    uint32_t rcu_mask;          
    IRQn_Type irqn;             
} i2c_conf_t;
 
typedef struct {
    gpio_t pin;             
    uint8_t cc_chan;        
} pwm_chan_t;
 
typedef struct {
    TIMER_Type *dev;                        
    uint32_t rcu_mask;                      
    uint32_t remap;                         
    pwm_chan_t chan[TIMER_CHANNEL_NUMOF];   
    gpio_af_t af;                           
    uint8_t bus;                            
} pwm_conf_t;
 
#define NWDT_TIME_LOWER_LIMIT           (1)
/* Ensure the internal "count" variable stays within the uint32 bounds.
   This variable corresponds to max_time * RTC_FREQ / MS_PER_SEC. On fe310,
   RTC_FREQ is 32768Hz. The 15 right shift is equivalent to a division by RTC_FREQ.
 */
#define NWDT_TIME_UPPER_LIMIT           ((UINT32_MAX >> 15)  * MS_PER_SEC + 1)
#define WDT_INTR_PRIORITY               (PLIC_NUM_PRIORITIES)
 
#define WDT_HAS_STOP                    (0)
 
#define RTT_DEV             RTC             
#define RTT_IRQ             RTC_ALARM_IRQn  
#define RTT_IRQ_PRIORITY    (2)             
#define RTT_MAX_VALUE       (0xffffffff)    
#define RTT_MIN_FREQUENCY   (1U)            
#define USBDEV_SET_ADDR_AFTER_STATUS    0   
#define USBDEV_NUM_ENDPOINTS            4   
void periph_clk_en(bus_t bus, uint32_t mask);
 
void periph_clk_dis(bus_t bus, uint32_t mask);
 
uint32_t periph_apb_clk(bus_t bus);
 
void gpio_init_af(gpio_t pin, gpio_af_t af);
 
void gd32vf103_clock_init(void);
void gd32v_enable_irc8(void);
void gd32v_disable_irc8(void);
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */