periph_cpu.h
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1/*
2 * Copyright (C) 2015-2017 Freie Universit├Ąt Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef PERIPH_CPU_H
21#define PERIPH_CPU_H
22
23#include "kernel_defines.h"
24#include "mutex.h"
25
26#include "cpu.h"
27#include "cpu_conf.h"
28
29#if defined(_SILICON_LABS_32B_SERIES_2)
30#include "em_iadc.h"
31#else
32#include "em_adc.h"
33#endif
34#include "em_cmu.h"
35#include "em_device.h"
36#include "em_gpio.h"
37#include "em_timer.h"
38#include "em_usart.h"
39#include "em_wdog.h"
40#include "em_rtc.h"
41#if defined(_SILICON_LABS_32B_SERIES_0)
42#include "em_dac.h"
43#elif defined (_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2)
44#include "em_vdac.h"
45#endif
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
54typedef struct {
55 CMU_Clock_TypeDef clk;
56 CMU_Select_TypeDef src;
57} clk_mux_t;
58
62typedef struct {
63 CMU_Clock_TypeDef clk;
64 CMU_ClkDiv_TypeDef div;
65} clk_div_t;
66
67
71#define CPUID_LEN (8U)
72
76#define CLOCK_CORECLOCK SystemCoreClock
77
78#if defined(DAC_COUNT) && DAC_COUNT > 0
82typedef struct {
83 DAC_TypeDef *dev;
84 DAC_Ref_TypeDef ref;
85 CMU_Clock_TypeDef cmu;
87
91typedef struct {
92 uint8_t dev;
93 uint8_t index;
94} dac_chan_conf_t;
95
96#elif defined(VDAC_COUNT) && VDAC_COUNT > 0
100typedef struct {
101 VDAC_TypeDef *dev;
102 VDAC_Ref_TypeDef ref;
103 CMU_Clock_TypeDef cmu;
104} dac_conf_t;
105
109typedef struct {
110 uint8_t dev;
111 uint8_t index;
112} dac_chan_conf_t;
113#endif
114
119/* RTT_MAX_VALUE some are 24bit, some are 32bit */
120#if defined(_RTC_CNT_MASK)
121#define RTT_MAX_VALUE _RTC_CNT_MASK /* mask has all bits set ==> MAX*/
122#elif defined(_RTCC_CNT_MASK)
123#define RTT_MAX_VALUE _RTCC_CNT_MASK /* mask has all bits set ==> MAX*/
124#endif
125#define RTT_MAX_FREQUENCY (32768U) /* in Hz */
126#define RTT_MIN_FREQUENCY (1U) /* in Hz */
127#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz, LFCLK*/
128
135#define HAVE_GPIO_T
136typedef uint32_t gpio_t;
142#define GPIO_UNDEF (0xffffffff)
143
147#define GPIO_PIN(x, y) ((gpio_t) ((x << 4) | y))
148
152#define GPIO_MODE(x, y) ((x << 1) | y)
153
157enum {
158#if (_GPIO_PORT_A_PIN_COUNT > 0)
159 PA = gpioPortA,
160#endif
161#if (_GPIO_PORT_B_PIN_COUNT > 0)
162 PB = gpioPortB,
163#endif
164#if (_GPIO_PORT_C_PIN_COUNT > 0)
165 PC = gpioPortC,
166#endif
167#if (_GPIO_PORT_D_PIN_COUNT > 0)
168 PD = gpioPortD,
169#endif
170#if (_GPIO_PORT_E_PIN_COUNT > 0)
171 PE = gpioPortE,
172#endif
173#if (_GPIO_PORT_F_PIN_COUNT > 0)
174 PF = gpioPortF,
175#endif
176#if (_GPIO_PORT_G_PIN_COUNT > 0)
177 PG = gpioPortG,
178#endif
179#if (_GPIO_PORT_H_PIN_COUNT > 0)
180 PH = gpioPortH,
181#endif
182#if (_GPIO_PORT_I_PIN_COUNT > 0)
183 PI = gpioPortI,
184#endif
185#if (_GPIO_PORT_J_PIN_COUNT > 0)
186 PJ = gpioPortJ,
187#endif
188#if (_GPIO_PORT_K_PIN_COUNT > 0)
189 PK = gpioPortK
190#endif
191};
192
193#ifndef DOXYGEN
198#define HAVE_GPIO_MODE_T
199typedef enum {
200 GPIO_IN = GPIO_MODE(gpioModeInput, 0),
201 GPIO_IN_PD = GPIO_MODE(gpioModeInputPull, 0),
202 GPIO_IN_PU = GPIO_MODE(gpioModeInputPull, 1),
203 GPIO_OUT = GPIO_MODE(gpioModePushPull, 0),
204 GPIO_OD = GPIO_MODE(gpioModeWiredAnd, 1),
205 GPIO_OD_PU = GPIO_MODE(gpioModeWiredAndPullUp, 1),
213#define HAVE_GPIO_FLANK_T
214typedef enum {
215 GPIO_FALLING = 2,
216 GPIO_RISING = 1,
217 GPIO_BOTH = 3
220#endif /* ndef DOXYGEN */
221
222#if defined(_SILICON_LABS_32B_SERIES_2)
230#if defined(_IADC_CFG_DIGAVG_MASK)
231#define ADC_MODE(osr, avg, res) ((osr << 16) | (avg << 8) | res)
232#else
233#define ADC_MODE(osr, res) ((osr << 16) | res)
234#endif
235
239#define ADC_MODE_OSR(mode) ((mode & 0xff0000) >> 16)
240
241#if defined(_IADC_CFG_DIGAVG_MASK)
245#define ADC_MODE_AVG(mode) ((mode & 0x00ff00) >> 8)
246#endif
247
251#define ADC_MODE_RES(mode) ((mode & 0x0000ff) >> 0)
252
257#define HAVE_ADC_RES_T
258#if defined(_IADC_CFG_DIGAVG_MASK)
259typedef enum {
260 ADC_RES_6BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 6),
261 ADC_RES_8BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 8),
262 ADC_RES_10BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 10),
263 ADC_RES_12BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 12),
264 ADC_RES_14BIT = ADC_MODE(iadcCfgOsrHighSpeed8x, iadcDigitalAverage1, 14),
265 ADC_RES_16BIT = ADC_MODE(iadcCfgOsrHighSpeed16x, iadcDigitalAverage2, 16),
266} adc_res_t;
267#else
268typedef enum {
269 ADC_RES_6BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 6),
270 ADC_RES_8BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 8),
271 ADC_RES_10BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 10),
272 ADC_RES_12BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 12),
273 ADC_RES_14BIT = ADC_MODE(iadcCfgOsrHighSpeed8x, 14),
274 ADC_RES_16BIT = ADC_MODE(iadcCfgOsrHighSpeed32x, 16),
275} adc_res_t;
276#endif
277
281typedef struct {
285 IADC_TypeDef *dev;
286
290 CMU_Clock_TypeDef cmu;
291
295 IADC_CfgReference_t reference;
296
302 uint32_t reference_mV;
303
310 IADC_CfgAnalogGain_t gain;
311
319 adc_res_t available_res[IADC0_CONFIGNUM];
320} adc_conf_t;
321
325typedef struct {
329 uint8_t dev;
330
334 gpio_t input_pos;
335
345 gpio_t input_neg;
347#else /* defined(_SILICON_LABS_32B_SERIES_2) */
352#define ADC_MODE(x, y) ((y << 4) | x)
353
357#define ADC_MODE_UNDEF(x) (ADC_MODE(x, 15))
358
359#ifndef DOXYGEN
364#define HAVE_ADC_RES_T
365typedef enum {
366 ADC_RES_6BIT = ADC_MODE(adcRes6Bit, 0),
367 ADC_RES_8BIT = ADC_MODE(adcRes8Bit, 0),
368 ADC_RES_10BIT = ADC_MODE(adcRes12Bit, 2),
369 ADC_RES_12BIT = ADC_MODE(adcRes12Bit, 0),
372} adc_res_t;
374#endif /* ndef DOXYGEN */
375
379typedef struct {
380 ADC_TypeDef *dev;
381 CMU_Clock_TypeDef cmu;
382} adc_conf_t;
383
387typedef struct {
388 uint8_t dev;
389#if defined(_SILICON_LABS_32B_SERIES_0)
390 ADC_SingleInput_TypeDef input;
391#elif defined(_SILICON_LABS_32B_SERIES_1)
392 ADC_PosSel_TypeDef input;
393#endif
394 ADC_Ref_TypeDef reference;
395 ADC_AcqTime_TypeDef acq_time;
397#endif /* !defined(_SILICON_LABS_32B_SERIES_2) */
398
403#define HAVE_HWCRYPTO_AES128
404#ifdef AES_CTRL_AES256
405#define HAVE_HWCRYPTO_AES256
406#endif
407#if defined(_SILICON_LABS_32B_SERIES_1)
408#define HAVE_HWCRYPTO_SHA1
409#define HAVE_HWCRYPTO_SHA256
410#endif
413#ifndef DOXYGEN
418#define HAVE_I2C_SPEED_T
419typedef enum {
420 I2C_SPEED_LOW = 10000,
421 I2C_SPEED_NORMAL = 100000,
422 I2C_SPEED_FAST = 400000,
423 I2C_SPEED_FAST_PLUS = 1000000,
424 I2C_SPEED_HIGH = 3400000,
427#endif /* ndef DOXYGEN */
428
432typedef struct {
433 I2C_TypeDef *dev;
434 gpio_t sda_pin;
435 gpio_t scl_pin;
436#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
437 uint32_t loc;
438#endif
439 CMU_Clock_TypeDef cmu;
441 uint32_t speed;
442} i2c_conf_t;
443
448#define PERIPH_I2C_NEED_READ_REG
449#define PERIPH_I2C_NEED_WRITE_REG
452#ifndef DOXYGEN
457#define HAVE_PWM_MODE_T
458typedef enum {
459 PWM_LEFT = timerModeUp, /*< use left aligned PWM */
460 PWM_RIGHT = timerModeDown, /*< use right aligned PWM */
461 PWM_CENTER = timerModeUp /*< not supported, use left aligned */
462} pwm_mode_t;
464#endif /* ndef DOXYGEN */
465
469typedef struct {
470 uint8_t index;
471 gpio_t pin;
472 uint32_t loc;
474
478typedef struct {
479 TIMER_TypeDef *dev;
480 CMU_Clock_TypeDef cmu;
482 uint8_t channels;
484} pwm_conf_t;
485
486#ifndef DOXYGEN
491#define HAVE_SPI_MODE_T
492typedef enum {
493 SPI_MODE_0 = usartClockMode0,
494 SPI_MODE_1 = usartClockMode1,
495 SPI_MODE_2 = usartClockMode2,
496 SPI_MODE_3 = usartClockMode3
497} spi_mode_t;
504#define HAVE_SPI_CLK_T
505typedef enum {
506 SPI_CLK_100KHZ = 100000,
507 SPI_CLK_400KHZ = 400000,
508 SPI_CLK_1MHZ = 1000000,
509 SPI_CLK_5MHZ = 5000000,
510 SPI_CLK_10MHZ = 10000000
511} spi_clk_t;
513#endif /* ndef DOXYGEN */
514
518typedef struct {
519 USART_TypeDef *dev;
520 gpio_t mosi_pin;
521 gpio_t miso_pin;
522 gpio_t clk_pin;
523#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
524 uint32_t loc;
525#endif
526 CMU_Clock_TypeDef cmu;
528} spi_dev_t;
529
534#define PERIPH_SPI_NEEDS_INIT_CS
535#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
536#define PERIPH_SPI_NEEDS_TRANSFER_REG
537#define PERIPH_SPI_NEEDS_TRANSFER_REGS
548#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
549typedef struct {
550 void *dev;
551 CMU_Clock_TypeDef cmu;
553#endif
554
555typedef struct {
556#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
561#else
562 void *dev;
563 CMU_Clock_TypeDef cmu;
564 IRQn_Type irq;
565#endif
567
568#define LETIMER_MAX_VALUE _LETIMER_TOP_MASK
569#define TIMER_MAX_VALUE _TIMER_TOP_MASK
575#ifndef CONFIG_EFM32_XTIMER_USE_LETIMER
576#define CONFIG_EFM32_XTIMER_USE_LETIMER 0
577#endif
578
582#ifndef DOXYGEN
586#define UART_MODE_UNSUPPORTED 0xf0
587
592#define HAVE_UART_PARITY_T
593#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
594typedef enum {
596 UART_PARITY_ODD = 1,
601#else
602typedef enum {
605 UART_PARITY_ODD = 3,
606 UART_PARITY_MARK = UART_MODE_UNSUPPORTED | 0,
607 UART_PARITY_SPACE = UART_MODE_UNSUPPORTED | 1,
609#endif
616#define HAVE_UART_DATA_BITS_T
617#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
618typedef enum {
624#else
625typedef enum {
626 UART_DATA_BITS_5 = UART_MODE_UNSUPPORTED | 0,
627 UART_DATA_BITS_6 = UART_MODE_UNSUPPORTED | 1,
631#endif
638#define HAVE_UART_STOP_BITS_T
639#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
640typedef enum {
644#else
645typedef enum {
649#endif
651#endif /* ndef DOXYGEN */
652
653typedef struct {
654 void *dev;
655 gpio_t rx_pin;
656 gpio_t tx_pin;
657#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
658 uint32_t loc;
659#endif
660 CMU_Clock_TypeDef cmu;
663
667#define PROVIDES_PM_OFF
668
672#define PROVIDES_PM_LAYERED_OFF
673
677#define PM_NUM_MODES (3U)
678
683#define EFM32_PM_MODE_EM3 (0U)
684#define EFM32_PM_MODE_EM2 (1U)
685#define EFM32_PM_MODE_EM1 (2U)
692#define WDT_CLOCK_HZ (1000U)
693
694#define NWDT_TIME_LOWER_LIMIT ((1U << (3U + wdogPeriod_9)) + 1U)
695#define NWDT_TIME_UPPER_LIMIT ((1U << (3U + wdogPeriod_256k)) + 1U)
696
697#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2)
698#define WDT_TIME_LOWER_LIMIT NWDT_TIME_LOWER_LIMIT
699#define WDT_TIME_UPPER_LIMIT NWDT_TIME_UPPER_LIMIT
700#endif
701
702#define WDT_HAS_STOP (1U)
709#define USBDEV_NUM_ENDPOINTS 7
712/* GPIO_LL's overrides */
713#ifndef DOXYGEN
714
715/* Not supported by hardware */
716#define HAVE_GPIO_SLEW_T
717typedef enum {
719 GPIO_SLEW_SLOW = 0,
720 GPIO_SLEW_FAST = 0,
723
724/* Not supported by hardware */
725#define HAVE_GPIO_PULL_STRENGTH_T
726typedef enum {
728 GPIO_PULL_WEAK = 0,
732
733/* Not implemented, see gpio_ll_arch.h comments */
734#define HAVE_GPIO_DRIVE_STRENGTH_T
735typedef enum {
737 GPIO_DRIVE_WEAK = 0,
741
742#endif
743
744#ifdef __cplusplus
745}
746#endif
747
748#endif /* PERIPH_CPU_H */
gpio_flank_t
Definition: periph_cpu.h:180
@ GPIO_OUT
select GPIO MASK as output
Definition: periph_cpu.h:165
@ GPIO_IN
select GPIO MASK as input
Definition: periph_cpu.h:164
i2c_speed_t
Definition: periph_cpu.h:276
spi_clk_t
Definition: periph_cpu.h:352
pwm_mode_t
Definition: periph_conf.h:220
gpio_t adc_conf_t
ADC configuration wrapper.
Definition: periph_cpu.h:337
#define GPIO_MODE(x, y)
Internal macro for combining pin mode (x) and pull-up/down (y).
Definition: periph_cpu.h:152
#define ADC_MODE(x, y)
Internal macro for combining ADC resolution (x) with number of shifts (y).
Definition: periph_cpu.h:352
#define ADC_MODE_UNDEF(x)
Internal define to note that resolution is not supported.
Definition: periph_cpu.h:357
enum IRQn IRQn_Type
Interrupt Number Definition.
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:93
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition: adc.h:99
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition: adc.h:95
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition: adc.h:98
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition: adc.h:94
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition: adc.h:96
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition: adc.h:97
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition: gpio_ll.h:216
gpio_slew_t
Enumeration of slew rate settings.
Definition: gpio_ll.h:280
gpio_drive_strength_t
Enumeration of drive strength options.
Definition: gpio_ll.h:247
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition: gpio_ll.h:217
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition: gpio_ll.h:218
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition: gpio_ll.h:219
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition: gpio_ll.h:220
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition: gpio_ll.h:281
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition: gpio_ll.h:284
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition: gpio_ll.h:283
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition: gpio_ll.h:285
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition: gpio_ll.h:250
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition: gpio_ll.h:249
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition: gpio_ll.h:251
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition: gpio_ll.h:248
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
@ GPIO_FALLING
emit interrupt on falling flank
Definition: periph_cpu.h:93
@ GPIO_RISING
emit interrupt on rising flank
Definition: periph_cpu.h:94
@ GPIO_BOTH
emit interrupt on both flanks
Definition: periph_cpu.h:95
@ GPIO_OD
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
@ GPIO_IN_PD
configure as input with pull-down resistor
Definition: gpio.h:120
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition: periph_cpu.h:280
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition: periph_cpu.h:277
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition: periph_cpu.h:282
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: periph_cpu.h:279
@ PWM_CENTER
center aligned
Definition: periph_conf.h:223
@ PWM_LEFT
left aligned
Definition: periph_conf.h:221
@ PWM_RIGHT
right aligned
Definition: periph_conf.h:222
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition: periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition: periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition: periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition: periph_cpu.h:47
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition: periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition: periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition: periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition: periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition: periph_cpu.h:353
@ UART_PARITY_SPACE
space parity
Definition: periph_cpu.h:507
@ UART_PARITY_NONE
no parity
Definition: periph_cpu.h:503
@ UART_PARITY_EVEN
even parity
Definition: periph_cpu.h:504
@ UART_PARITY_ODD
odd parity
Definition: periph_cpu.h:505
@ UART_PARITY_MARK
mark parity
Definition: periph_cpu.h:506
@ UART_STOP_BITS_2
2 stop bits
Definition: periph_cpu.h:536
@ UART_STOP_BITS_1
1 stop bit
Definition: periph_cpu.h:535
@ UART_DATA_BITS_6
6 data bits
Definition: periph_cpu.h:520
@ UART_DATA_BITS_5
5 data bits
Definition: periph_cpu.h:519
@ UART_DATA_BITS_7
7 data bits
Definition: periph_cpu.h:521
@ UART_DATA_BITS_8
8 data bits
Definition: periph_cpu.h:522
Common macros and compiler attributes/pragmas configuration.
spi_mode_t
Support SPI modes.
Definition: periph_cpu.h:43
Mutex for thread synchronization.
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:82
uart_parity_t
Definition of possible parity modes.
Definition: periph_cpu.h:502
uart_stop_bits_t
Definition of possible stop bits lengths.
Definition: periph_cpu.h:534
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition: periph_cpu.h:518
@ PB
port B
Definition: periph_cpu.h:136
@ PC
port C
Definition: periph_cpu.h:137
@ PA
port A
Definition: periph_cpu.h:135
@ PD
port D
Definition: periph_cpu.h:138
Implementation specific CPU configuration options.
ADC channel configuration.
Definition: periph_cpu.h:387
ADC_AcqTime_TypeDef acq_time
channel acquisition time
Definition: periph_cpu.h:395
uint8_t dev
device index
Definition: periph_cpu.h:388
ADC_Ref_TypeDef reference
channel voltage reference
Definition: periph_cpu.h:394
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:380
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:381
Clock divider configuration.
Definition: periph_cpu.h:62
CMU_ClkDiv_TypeDef div
Divisor.
Definition: periph_cpu.h:64
CMU_Clock_TypeDef clk
Clock domain.
Definition: periph_cpu.h:63
Clock mux configuration.
Definition: periph_cpu.h:54
CMU_Select_TypeDef src
Source clock.
Definition: periph_cpu.h:56
CMU_Clock_TypeDef clk
Clock domain.
Definition: periph_cpu.h:55
DAC line configuration data.
Definition: periph_cpu.h:238
I2C configuration structure.
Definition: periph_cpu.h:299
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:439
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:433
uint32_t speed
the bus speed
Definition: periph_cpu.h:441
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:440
PWM channel configuration.
Definition: periph_cpu.h:469
uint32_t loc
location of the pin
Definition: periph_cpu.h:472
uint8_t index
TIMER channel to use.
Definition: periph_cpu.h:470
gpio_t pin
pin used for pwm
Definition: periph_cpu.h:471
PWM device configuration.
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:481
const pwm_chan_conf_t * channel
pointer to first channel config
Definition: periph_cpu.h:483
TIMER_TypeDef * dev
TIMER device used.
Definition: periph_cpu.h:479
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:480
uint8_t channels
the number of available channels
Definition: periph_cpu.h:482
SPI device configuration.
Definition: periph_cpu.h:518
gpio_t clk_pin
pin used for CLK
Definition: periph_cpu.h:522
gpio_t mosi_pin
pin used for MOSI
Definition: periph_cpu.h:520
USART_TypeDef * dev
USART device used.
Definition: periph_cpu.h:519
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:526
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:527
gpio_t miso_pin
pin used for MISO
Definition: periph_cpu.h:521
Timer device configuration.
Definition: periph_cpu.h:264
IRQn_Type irq
number of the higher timer IRQ channel
Definition: periph_cpu.h:559
timer_dev_t prescaler
the lower neighboring timer (not initialized for LETIMER)
Definition: periph_cpu.h:557
timer_dev_t timer
the higher numbered timer
Definition: periph_cpu.h:558
uint8_t channel_numof
number of channels per timer
Definition: periph_cpu.h:560
Define timer configuration values.
Definition: periph_cpu.h:549
void * dev
TIMER_TypeDef or LETIMER_TypeDef device used.
Definition: periph_cpu.h:550
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:551
UART device configuration.
Definition: periph_cpu.h:218
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:660
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:661
uint32_t loc
location of UART pins
Definition: periph_cpu.h:658
void * dev
UART, USART or LEUART device used.
Definition: periph_cpu.h:654