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periph_cpu.h
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1/*
2 * SPDX-FileCopyrightText: 2021 Otto-von-Guericke-Universität Magdeburg
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "cpu.h"
20#include "vendor/RP2040.h"
21#include "io_reg.h"
22#include "macros/units.h"
23#include "periph/pio.h" /* pio_t */
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#if !defined(PLL_SYS_REF_DIV) || defined(DOXYGEN)
35#define PLL_SYS_REF_DIV 1
36#endif
37
38#if !defined(PLL_USB_REF_DIV) || defined(DOXYGEN)
42#define PLL_USB_REF_DIV 1
43#endif
44
45#if !defined(PLL_SYS_VCO_FEEDBACK_SCALE) || defined(DOXYGEN)
52#define PLL_SYS_VCO_FEEDBACK_SCALE 125
53#endif
54
55#if !defined(PLL_SYS_POSTDIV1) || defined(DOXYGEN)
61#define PLL_SYS_POSTDIV1 6
62#endif
63
64#if !defined(PLL_SYS_POSTDIV2) || defined(DOXYGEN)
70#define PLL_SYS_POSTDIV2 2
71#endif
72
73#if !defined(PLL_USB_VCO_FEEDBACK_SCALE) || defined(DOXYGEN)
80#define PLL_USB_VCO_FEEDBACK_SCALE 40
81#endif
82
83#if !defined(PLL_USB_POSTDIV1) || defined(DOXYGEN)
89#define PLL_USB_POSTDIV1 5
90#endif
91
92#if !defined(PLL_USB_POSTDIV2) || defined(DOXYGEN)
98#define PLL_USB_POSTDIV2 2
99#endif
100
101#if !defined(CLOCK_XOSC) || defined(DOXYGEN)
106#define CLOCK_XOSC MHZ(12)
107#endif
108
112#define PLL_CLOCK(vco_feedback, postdiv1, postdiv2) \
113 (CLOCK_XOSC * (vco_feedback) / (postdiv1) / (postdiv2))
114
118#define CLOCK_CORECLOCK \
119 PLL_CLOCK(PLL_SYS_VCO_FEEDBACK_SCALE, PLL_SYS_POSTDIV1, PLL_SYS_POSTDIV2)
120
124#define CLOCK_USB \
125 PLL_CLOCK(PLL_USB_VCO_FEEDBACK_SCALE, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2)
126
131#define CLOCK_XOSC_MAX MHZ(15)
132#define CLOCK_XOSC_MIN MHZ(5)
133#define PLL_POSTDIV_MIN (1U)
134#define PLL_POSTDIV_MAX (7U)
135#define PLL_VCO_FEEDBACK_SCALE_MIN (16U)
136#define PLL_VCO_FEEDBACK_SCALE_MAX (320U)
137#define PLL_REF_DIV_MIN (1U)
139#define PLL_REF_DIV_MAX (1U)
142
143#if CLOCK_USB != MHZ(48)
144#error "USB clock != 48 MHz, check PLL_USB_VCO_FEEDBACK_SCALE, PLL_USB_POSTDIV1, PLL_SYS_POSTDIV2"
145#endif
146
147#if (CLOCK_XOSC > CLOCK_XOSC_MAX) || (CLOCK_XOSC < CLOCK_XOSC_MIN)
148#error "Value for CLOCK_XOSC out of range, check config"
149#endif
150
151#if (PLL_SYS_REF_DIV < PLL_REF_DIV_MIN) || (PLL_SYS_REF_DIV > PLL_REF_DIV_MAX)
152#error "Value for PLL_SYS_REF_DIV out of range, check config"
153#endif
154
155#if (PLL_USB_REF_DIV < PLL_REF_DIV_MIN) || (PLL_USB_REF_DIV > PLL_REF_DIV_MAX)
156#error "Value for PLL_USB_REF_DIV out of range, check config"
157#endif
158
159#if (PLL_SYS_VCO_FEEDBACK_SCALE < PLL_VCO_FEEDBACK_SCALE_MIN) \
160 || (PLL_SYS_VCO_FEEDBACK_SCALE > PLL_VCO_FEEDBACK_SCALE_MAX)
161#error "Value for PLL_SYS_VCO_FEEDBACK_SCALE out of range, check config"
162#endif
163
164#if (PLL_USB_VCO_FEEDBACK_SCALE < PLL_VCO_FEEDBACK_SCALE_MIN) \
165 || (PLL_USB_VCO_FEEDBACK_SCALE > PLL_VCO_FEEDBACK_SCALE_MAX)
166#error "Value for PLL_USB_VCO_FEEDBACK_SCALE out of range, check config"
167#endif
168
169#if (PLL_SYS_POSTDIV1 < PLL_POSTDIV_MIN) || (PLL_SYS_POSTDIV1 > PLL_POSTDIV_MAX)
170#error "Value for PLL_SYS_POSTDIV1 out of range, check config"
171#endif
172
173#if (PLL_SYS_POSTDIV2 < PLL_POSTDIV_MIN) || (PLL_SYS_POSTDIV2 > PLL_POSTDIV_MAX)
174#error "Value for PLL_SYS_POSTDIV2 out of range, check config"
175#endif
176
177#if (PLL_USB_POSTDIV1 < PLL_POSTDIV_MIN) || (PLL_USB_POSTDIV1 > PLL_POSTDIV_MAX)
178#error "Value for PLL_USB_POSTDIV1 out of range, check config"
179#endif
180
181#if (PLL_USB_POSTDIV2 < PLL_POSTDIV_MIN) || (PLL_USB_POSTDIV2 > PLL_POSTDIV_MAX)
182#error "Value for PLL_USB_POSTDIV2 out of range, check config"
183#endif
184
185#if !defined(CLOCK_PERIPH_SOURCE) || defined(DOXYGEN)
189#define CLOCK_PERIPH_SOURCE CLOCKS_CLK_PERI_CTRL_AUXSRC_clk_sys
190#endif
191
192#if !defined(CLOCK_PERIPH) || defined(DOXYGEN)
196#define CLOCK_PERIPH CLOCK_CORECLOCK
197#endif
198
202#define RESETS_RESET_MASK \
203 (RESETS_RESET_usbctrl_Msk | \
204 RESETS_RESET_uart1_Msk | \
205 RESETS_RESET_uart0_Msk | \
206 RESETS_RESET_timer_Msk | \
207 RESETS_RESET_tbman_Msk | \
208 RESETS_RESET_sysinfo_Msk | \
209 RESETS_RESET_syscfg_Msk | \
210 RESETS_RESET_spi1_Msk | \
211 RESETS_RESET_spi0_Msk | \
212 RESETS_RESET_rtc_Msk | \
213 RESETS_RESET_pwm_Msk | \
214 RESETS_RESET_pll_usb_Msk | \
215 RESETS_RESET_pll_sys_Msk | \
216 RESETS_RESET_pio1_Msk | \
217 RESETS_RESET_pio0_Msk | \
218 RESETS_RESET_pads_qspi_Msk | \
219 RESETS_RESET_pads_bank0_Msk | \
220 RESETS_RESET_jtag_Msk | \
221 RESETS_RESET_io_qspi_Msk | \
222 RESETS_RESET_io_bank0_Msk | \
223 RESETS_RESET_i2c1_Msk | \
224 RESETS_RESET_i2c0_Msk | \
225 RESETS_RESET_dma_Msk | \
226 RESETS_RESET_busctrl_Msk | \
227 RESETS_RESET_adc_Msk)
228
235#define GPIO_PIN(port, pin) ((((port) & 0)) | (pin))
236
241#define HAVE_GPIO_T
242typedef uint32_t gpio_t;
244
248#define GPIO_UNDEF UINT32_MAX
249
254#define HAVE_GPIO_FLANK_T
255typedef enum {
258 GPIO_FALLING = 0x4,
259 GPIO_RISING = 0x8,
260 GPIO_BOTH = 0xc
262
263
271#define GPIO_PAD_REGISTER_RESET_VALUE (0x00000056)
275enum {
281};
282
286typedef struct {
287 uint32_t slew_rate_fast : 1;
288 uint32_t schmitt_trig_enable : 1;
289 uint32_t pull_down_enable : 1;
290 uint32_t pull_up_enable : 1;
291 uint32_t drive_strength : 2;
292 uint32_t input_enable : 1;
293 uint32_t output_disable : 1;
295 uint32_t : 24;
297
298
306#define GPIO_IO_REGISTER_RESET_VALUE (0x0000001f)
328
332enum {
338};
339
343enum {
349};
350
354enum {
360};
361
365enum {
371};
372
376typedef struct {
377 uint32_t function_select : 5;
378 uint32_t : 3;
379 uint32_t output_override : 2;
380 uint32_t : 2;
382 uint32_t : 2;
383 uint32_t input_override : 2;
384 uint32_t : 10;
385 uint32_t irq_override : 2;
386 uint32_t : 2;
388
389
393typedef struct {
394 gpio_t pin;
395 uint8_t chan;
396} adc_conf_t;
397
401#define PWM_SLICE_NUMOF (8)
402
406#define PWM_CHANNEL_NUMOF (2)
407
411typedef struct {
412 gpio_t pin;
413 uint8_t cc_chan;
414} pwm_chan_t;
415
419typedef struct {
420 uint8_t pwm_slice;
424} pwm_conf_t;
425
429typedef struct {
430 UART0_Type *dev;
431 gpio_t rx_pin;
432 gpio_t tx_pin;
435
439#define PERIPH_TIMER_PROVIDES_SET
440
447
453typedef struct {
454 TIMER_Type *dev;
456 uint8_t ch_numof;
458
462typedef struct {
463 PIO0_Type *dev;
466} pio_conf_t;
467
471typedef struct {
473 gpio_t sda;
474 gpio_t scl;
475 unsigned irq;
477
483static inline volatile uint32_t * gpio_pad_register(uint8_t pin)
484{
485 return (uint32_t *)(PADS_BANK0_BASE + 4 + (pin << 2));
486}
487
492static inline void gpio_set_pad_config(uint8_t pin, gpio_pad_ctrl_t config)
493{
494 uint32_t *c = (uint32_t *)&config;
495 *gpio_pad_register(pin) = *c;
496}
497
501static inline volatile uint32_t * gpio_io_register(uint8_t pin)
502{
503 return (uint32_t *)(IO_BANK0_BASE + 4 + (pin << 3));
504}
505
510static inline void gpio_set_io_config(uint8_t pin, gpio_io_ctrl_t config)
511{
512 uint32_t *c = (uint32_t *)&config;
513 *gpio_io_register(pin) = *c;
514}
515
519static inline void gpio_set_function_select(uint8_t pin, gpio_function_select_t funcsel)
520{
521 io_reg_write_dont_corrupt(gpio_io_register(pin), funcsel << IO_BANK0_GPIO0_CTRL_FUNCSEL_Pos,
522 IO_BANK0_GPIO0_CTRL_FUNCSEL_Msk);
523}
524
533
540static inline void periph_reset(uint32_t components)
541{
542 io_reg_atomic_set(&RESETS->RESET, components);
543}
544
551static inline void periph_reset_done(uint32_t components)
552{
553 io_reg_atomic_clear(&RESETS->RESET, components);
554 while ((~RESETS->RESET_DONE) & components) { }
555}
556
561
570void clock_sys_configure_source(uint32_t f_in, uint32_t f_out,
571 CLOCKS_CLK_SYS_CTRL_SRC_Enum source);
572
583void clock_sys_configure_aux_source(uint32_t f_in, uint32_t f_out,
584 CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum aux);
585
596void clock_ref_configure_source(uint32_t f_in, uint32_t f_out,
597 CLOCKS_CLK_REF_CTRL_SRC_Enum source);
598
609void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out,
610 CLOCKS_CLK_REF_CTRL_AUXSRC_Enum aux);
611
618void clock_periph_configure(CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum aux);
619
630void clock_gpout0_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum aux);
631
642void clock_gpout1_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum aux);
643
654void clock_gpout2_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum aux);
655
666void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum aux);
667
674void clock_adc_configure(CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum aux);
676
681
693void pll_start_sys(uint8_t ref_div,
694 uint16_t vco_feedback_scale,
695 uint8_t post_div_1, uint8_t post_div_2);
696
708void pll_start_usb(uint8_t ref_div,
709 uint16_t vco_feedback_scale,
710 uint8_t post_div_1, uint8_t post_div_2);
711
715void pll_stop_sys(void);
716
720void pll_stop_usb(void);
721
725void pll_reset_sys(void);
726
730void pll_reset_usb(void);
731
733
747void xosc_start(uint32_t f_ref);
748
752void xosc_stop(void);
753
755
760
767void rosc_start(void);
768
774void rosc_stop(void);
775
777
782#define HAVE_SPI_CLK_T
783enum {
789};
790
794typedef uint32_t spi_clk_t;
796
800typedef struct {
801 SPI0_Type *dev;
802 gpio_t miso_pin;
803 gpio_t mosi_pin;
804 gpio_t clk_pin;
805} spi_conf_t;
806
807#define PERIPH_SPI_NEEDS_TRANSFER_REG
808#define PERIPH_SPI_NEEDS_TRANSFER_REGS
809#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
810
811#ifdef __cplusplus
812}
813#endif
814
gpio_flank_t
Definition periph_cpu.h:176
spi_clk_t
Definition periph_cpu.h:348
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:353
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:352
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:350
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:351
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:349
void xosc_start(void)
Configures the Crystal to run.
High-level PIO peripheral driver interface.
gpio_function_select_t
Possible function values for gpio_io_ctrl_t::function_select.
Definition gpio_conf.h:29
@ FUNCTION_SELECT_PIO0
connect pin to the first PIO peripheral
Definition gpio_conf.h:46
@ FUNCTION_SELECT_CLOCK
connect pin to the timer (depending on pin: external clock, clock output, or not supported)
Definition gpio_conf.h:53
@ FUNCTION_SELECT_PIO1
connect pin to the second PIO peripheral
Definition gpio_conf.h:49
@ FUNCTION_SELECT_I2C
connect pin to the I2C peripheral (SCL/SDA depends on pin)
Definition gpio_conf.h:37
@ FUNCTION_SELECT_PWM
connect pin to the timer for PWM (channel depends on pin)
Definition gpio_conf.h:40
@ FUNCTION_SELECT_UART
connect pin to the UART peripheral (TXD/RXD depends on pin)
Definition gpio_conf.h:34
@ FUNCTION_SELECT_USB
connect pin to the USB peripheral (function depends on pin)
Definition gpio_conf.h:56
@ FUNCTION_SELECT_SIO
use pin as vanilla GPIO
Definition gpio_conf.h:43
@ FUNCTION_SELECT_SPI
connect pin to the SPI peripheral (MISO/MOSI/SCK depends on pin)
Definition gpio_conf.h:31
@ FUNCTION_SELECT_NONE
Reset value, pin unconnected.
Definition gpio_conf.h:59
enum IRQn IRQn_Type
Interrupt Number Definition.
unsigned pio_t
PIO index type.
Definition pio.h:75
RP2040 atomic register access macros.
static void io_reg_atomic_clear(volatile uint32_t *reg, uint32_t mask)
Clear the bits in the register at address reg as given by the set bits in operand op.
Definition io_reg.h:96
static void io_reg_write_dont_corrupt(volatile uint32_t *reg, uint32_t value, uint32_t mask)
Updates part of an I/O register without corrupting its contents.
Definition io_reg.h:124
static void io_reg_atomic_set(volatile uint32_t *reg, uint32_t mask)
Set the bits in the register at address reg as given by the set bits in operand op.
Definition io_reg.h:84
@ DRIVE_STRENGTH_NUMOF
number of different drive strength options
Definition periph_cpu.h:280
@ DRIVE_STRENGTH_4MA
set driver strength to 4 mA
Definition periph_cpu.h:277
@ DRIVE_STRENGTH_8MA
set driver strength to 8 mA
Definition periph_cpu.h:278
@ DRIVE_STRENGTH_12MA
set driver strength to 12 mA
Definition periph_cpu.h:279
@ DRIVE_STRENGTH_2MA
set driver strength to 2 mA
Definition periph_cpu.h:276
void rosc_start(void)
Start the ring oscillator in default mode.
void clock_gpout2_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum aux)
Configure gpio24 as clock output pin.
@ GPIO_LEVEL_LOW
emit interrupt level-triggered on low input
Definition periph_cpu.h:256
@ GPIO_LEVEL_HIGH
emit interrupt level-triggered on low input
Definition periph_cpu.h:257
@ OUTPUT_OVERRIDE_HIGH
drive pin high, overriding peripheral signal
Definition periph_cpu.h:336
@ OUTPUT_OVERRIDE_NORMAL
drive pin from connected peripheral
Definition periph_cpu.h:333
@ OUTPUT_OVERRIDE_LOW
drive pin low, overriding peripheral signal
Definition periph_cpu.h:335
@ OUTPUT_OVERRIDE_NUMOF
number of possible output override settings
Definition periph_cpu.h:337
@ OUTPUT_OVERRIDE_INVERT
drive pin from connected peripheral, but invert output
Definition periph_cpu.h:334
void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum aux)
Configure gpio25 as clock output pin.
static void gpio_set_pad_config(uint8_t pin, gpio_pad_ctrl_t config)
Convenience function to set the pad configuration of the given pin using the bit-field convenience ty...
Definition periph_cpu.h:492
static void gpio_reset_all_config(uint8_t pin)
Restore the default I/O and PAD configuration of the given GPIO pin.
Definition periph_cpu.h:528
void pll_start_usb(uint8_t ref_div, uint16_t vco_feedback_scale, uint8_t post_div_1, uint8_t post_div_2)
Start the PLL for the USB clock output[MHz] = f_ref / ref_div * vco_feedback_scale / post_div_1 / pos...
void pll_stop_sys(void)
Stop the PLL of the system clock.
void clock_adc_configure(CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum aux)
Configure the ADC clock to run from a dedicated auxiliary clock source.
static void gpio_set_function_select(uint8_t pin, gpio_function_select_t funcsel)
Set the function select subregister for the given pin to the given value.
Definition periph_cpu.h:519
void xosc_stop(void)
Stop the crystal.
#define GPIO_PAD_REGISTER_RESET_VALUE
Reset value of the GPIO pad configuration register.
Definition periph_cpu.h:271
void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_REF_CTRL_AUXSRC_Enum aux)
Configure the reference clock to run from an auxiliary clock source, like PLL.
#define PWM_CHANNEL_NUMOF
Number of channels available per slice.
Definition periph_cpu.h:406
static void gpio_set_io_config(uint8_t pin, gpio_io_ctrl_t config)
Convenience function to set the I/O configuration of the given pin using the bit-field convenience ty...
Definition periph_cpu.h:510
@ IRQ_OVERRIDE_INVERT
invert IRQ signal
Definition periph_cpu.h:367
@ IRQ_OVERRIDE_LOW
set IRQ signal to low
Definition periph_cpu.h:368
@ IRQ_OVERRIDE_NORMAL
don't mess with IRQ signal
Definition periph_cpu.h:366
@ IRQ_OVERRIDE_HIGH
set IRQ signal to high
Definition periph_cpu.h:369
@ IRQ_OVERRIDE_NUMOF
number of possible IRQ override settings
Definition periph_cpu.h:370
void clock_ref_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_REF_CTRL_SRC_Enum source)
Configure the reference clock to run from a clock source, which is either the ROSC or the XOSC.
void pll_stop_usb(void)
Stop the PLL of the USB clock.
@ OUTPUT_ENABLE_OVERRIDE_NUMOF
number of possible output enable override settings
Definition periph_cpu.h:348
@ OUTPUT_ENABLE_OVERRIDE_DISABLE
disable output, overriding peripheral signal
Definition periph_cpu.h:346
@ OUTPUT_ENABLE_OVERRIDE_NOMARL
enable output as specified by connected peripheral
Definition periph_cpu.h:344
@ OUTPUT_ENABLE_OVERRIDE_ENABLE
enable output, overriding peripheral signal
Definition periph_cpu.h:347
@ OUTPUT_ENABLE_OVERRIDE_INVERT
invert output enable setting of peripheral
Definition periph_cpu.h:345
void clock_sys_configure_aux_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum aux)
Configure the system clock to run from an auxiliary clock source, like PLL.
static volatile uint32_t * gpio_io_register(uint8_t pin)
Get the IO control register for the given GPIO pin as word.
Definition periph_cpu.h:501
static volatile uint32_t * gpio_pad_register(uint8_t pin)
Get the PAD control register for the given GPIO pin as word.
Definition periph_cpu.h:483
void pll_reset_sys(void)
Reset the PLL of the system clock.
void pll_reset_usb(void)
Reset the PLL of the USB clock.
void clock_sys_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_SYS_CTRL_SRC_Enum source)
Configure the system clock to run from the reference clock, which is the default on boot.
void clock_gpout1_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum aux)
Configure gpio23 as clock output pin.
void clock_gpout0_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum aux)
Configure gpio21 as clock output pin.
void pll_start_sys(uint8_t ref_div, uint16_t vco_feedback_scale, uint8_t post_div_1, uint8_t post_div_2)
Start the PLL for the system clock output[MHz] = f_ref / ref_div * vco_feedback_scale / post_div_1 / ...
@ INPUT_OVERRIDE_LOW
signal low to connected peripheral
Definition periph_cpu.h:357
@ INPUT_OVERRIDE_INVERT
invert signal to connected peripheral
Definition periph_cpu.h:356
@ INPUT_OVERRIDE_NUMOF
number of possible input override settings
Definition periph_cpu.h:359
@ INPUT_OVERRIDE_NOMARL
don't mess with peripheral input signal
Definition periph_cpu.h:355
@ INPUT_OVERRIDE_HIGH
signal high to connected peripheral
Definition periph_cpu.h:358
static void periph_reset_done(uint32_t components)
Waits until hardware components have been reset.
Definition periph_cpu.h:551
void clock_periph_configure(CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum aux)
Configure the peripheral clock to run from a dedicated auxiliary clock source.
#define GPIO_IO_REGISTER_RESET_VALUE
Reset value of the GPIO I/O configuration register.
Definition periph_cpu.h:306
void rosc_stop(void)
Turn off the ROSC to save power.
static void periph_reset(uint32_t components)
Reset hardware components.
Definition periph_cpu.h:540
ADC device configuration.
Definition periph_cpu.h:374
Memory layout of GPIO control register in IO bank 0.
Definition periph_cpu.h:376
uint32_t output_enable_override
output enable override
Definition periph_cpu.h:381
uint32_t input_override
input value override
Definition periph_cpu.h:383
uint32_t irq_override
interrupt inversion override
Definition periph_cpu.h:385
uint32_t output_override
output value override
Definition periph_cpu.h:379
uint32_t function_select
select GPIO function
Definition periph_cpu.h:377
Memory layout of GPIO control register in pads bank 0.
Definition periph_cpu.h:286
uint32_t pull_up_enable
enable pull up resistor
Definition periph_cpu.h:290
uint32_t schmitt_trig_enable
enable Schmitt trigger
Definition periph_cpu.h:288
uint32_t input_enable
enable as input
Definition periph_cpu.h:292
uint32_t slew_rate_fast
set slew rate control to fast
Definition periph_cpu.h:287
uint32_t output_disable
disable output, overwrite output enable from peripherals
Definition periph_cpu.h:293
uint32_t drive_strength
GPIO driver strength.
Definition periph_cpu.h:291
uint32_t pull_down_enable
enable pull down resistor
Definition periph_cpu.h:289
PIO configuration type.
Definition periph_cpu.h:462
IRQn_Type irqn0
PIO IRQ0 interrupt number.
Definition periph_cpu.h:464
IRQn_Type irqn1
PIO IRQ1 interrupt number.
Definition periph_cpu.h:465
PIO0_Type * dev
PIO device.
Definition periph_cpu.h:463
PIO I2C configuration type.
Definition periph_cpu.h:471
gpio_t sda
Pin to use as SDA pin.
Definition periph_cpu.h:473
pio_t pio
PIO number of the PIO to run this configuration.
Definition periph_cpu.h:472
unsigned irq
PIO IRQ line to use.
Definition periph_cpu.h:475
gpio_t scl
Pin to use as SCL pin.
Definition periph_cpu.h:474
PWM channel.
Definition periph_cpu.h:465
PWM device configuration.
uint8_t pwm_slice
PWM slice instance, must be < to PWM_SLICE_NUMOF.
Definition periph_cpu.h:420
pwm_chan_t chan[TIMER_CHANNEL_NUMOF]
channel mapping set to {GPIO_UNDEF, 0} if not used
Definition periph_cpu.h:479
SPI device configuration.
Definition periph_cpu.h:333
gpio_t miso_pin
pin used for MISO
Definition periph_cpu.h:337
gpio_t mosi_pin
pin used for MOSI
Definition periph_cpu.h:338
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:334
gpio_t clk_pin
GPIO pin to use for CLK.
Definition periph_cpu.h:804
Configuration type of a timer channel.
Definition periph_cpu.h:444
IRQn_Type irqn
timer channel interrupt number
Definition periph_cpu.h:445
Timer device configuration.
Definition periph_cpu.h:260
const timer_channel_conf_t * ch
pointer to timer channel configuration
Definition periph_cpu.h:455
uint8_t ch_numof
number of timer channels
Definition periph_cpu.h:456
UART device configuration.
Definition periph_cpu.h:214
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:215
uint8_t irqn
IRQ channel.
Definition periph_cpu.h:332
gpio_t tx_pin
pin used for TX
Definition periph_cpu.h:218
gpio_t rx_pin
pin used for RX
Definition periph_cpu.h:217
Unit helper macros.
#define MHZ(x)
A macro to return the Hz in x MHz.
Definition units.h:48
#define KHZ(x)
A macro to return the Hz in x kHz.
Definition units.h:43