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periph_cpu.h File Reference

RP2040 specific definitions for handling peripherals. More...

Detailed Description

RP2040 specific definitions for handling peripherals.

Author
Fabian Hüßler fabia.nosp@m.n.hu.nosp@m.essle.nosp@m.r@ov.nosp@m.gu.de
Marian Buschsieweke maria.nosp@m.n.bu.nosp@m.schsi.nosp@m.ewek.nosp@m.e@ovg.nosp@m.u.de

Definition in file periph_cpu.h.

#include "cpu.h"
#include "vendor/RP2040.h"
#include "io_reg.h"
#include "macros/units.h"
#include "periph/pio.h"
+ Include dependency graph for periph_cpu.h:

Go to the source code of this file.

Data Structures

struct  gpio_pad_ctrl_t
 Memory layout of GPIO control register in pads bank 0. More...
 
struct  gpio_io_ctrl_t
 Memory layout of GPIO control register in IO bank 0. More...
 
struct  adc_conf_t
 ADC device configuration. More...
 
struct  pwm_chan_t
 PWM channel. More...
 
struct  pwm_conf_t
 PWM device configuration. More...
 
struct  uart_conf_t
 UART device configuration. More...
 
struct  timer_channel_conf_t
 Configuration type of a timer channel. More...
 
struct  timer_conf_t
 Timer device configuration. More...
 
struct  pio_conf_t
 PIO configuration type. More...
 
struct  pio_i2c_conf_t
 PIO I2C configuration type. More...
 
struct  spi_conf_t
 SPI device configuration. More...
 

Macros

#define CLOCK_PERIPH_SOURCE   CLOCKS_CLK_PERI_CTRL_AUXSRC_clk_sys
 How to source the peripheral clock (default: 125 MHz system clock)
 
#define CLOCK_PERIPH   CLOCK_CORECLOCK
 Peripheral clock (by default source from system clock)
 
#define RESETS_RESET_MASK
 Periphery blocks that can be reset.
 
#define GPIO_PIN(port, pin)   ((((port) & 0)) | (pin))
 Convert (port, pin) tuple to a gpio_t value.
 
#define GPIO_UNDEF   UINT32_MAX
 Definition of a fitting UNDEF value.
 
#define PWM_SLICE_NUMOF   (8)
 Number of slices available per PWM device.
 
#define PWM_CHANNEL_NUMOF   (2)
 Number of channels available per slice.
 
#define PERIPH_TIMER_PROVIDES_SET
 Prevent shared timer functions from being used.
 
#define PERIPH_SPI_NEEDS_TRANSFER_REG
 
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
 

Functions

static volatile uint32_t * gpio_pad_register (uint8_t pin)
 Get the PAD control register for the given GPIO pin as word.
 
static void gpio_set_pad_config (uint8_t pin, gpio_pad_ctrl_t config)
 Convenience function to set the pad configuration of the given pin using the bit-field convenience type.
 
static volatile uint32_t * gpio_io_register (uint8_t pin)
 Get the IO control register for the given GPIO pin as word.
 
static void gpio_set_io_config (uint8_t pin, gpio_io_ctrl_t config)
 Convenience function to set the I/O configuration of the given pin using the bit-field convenience type.
 
static void gpio_set_function_select (uint8_t pin, gpio_function_select_t funcsel)
 Set the function select subregister for the given pin to the given value.
 
static void gpio_reset_all_config (uint8_t pin)
 Restore the default I/O and PAD configuration of the given GPIO pin.
 
static void periph_reset (uint32_t components)
 Reset hardware components.
 
static void periph_reset_done (uint32_t components)
 Waits until hardware components have been reset.
 
#define PLL_SYS_REF_DIV   1
 For generating the system clock via PLL, the XOSC reference clock can be divided.
 
#define PLL_USB_REF_DIV   1
 Same as PLL_SYS_REF_DIV but for the PLL generating the USB clock.
 
#define PLL_SYS_VCO_FEEDBACK_SCALE   125
 VCO feedback scale used for system clock.
 
#define PLL_SYS_POSTDIV1   6
 First post-PLL clock divider for system clock.
 
#define PLL_SYS_POSTDIV2   2
 Second post-PLL clock divider for system clock.
 
#define PLL_USB_VCO_FEEDBACK_SCALE   40
 VCO feedback scale used for USB clock.
 
#define PLL_USB_POSTDIV1   5
 First post-PLL clock divider for USB clock.
 
#define PLL_USB_POSTDIV2   2
 Second post-PLL clock divider for USB clock.
 
#define CLOCK_XOSC   MHZ(12)
 The RP2040 reference design attaches a 12 MHz crystal to the MCU, so we take this value as default.
 
#define PLL_CLOCK(vco_feedback, postdiv1, postdiv2)    (CLOCK_XOSC * (vco_feedback) / (postdiv1) / (postdiv2))
 Calculate the resulting PLL clock frequency for the given parameters.
 
#define CLOCK_CORECLOCK    PLL_CLOCK(PLL_SYS_VCO_FEEDBACK_SCALE, PLL_SYS_POSTDIV1, PLL_SYS_POSTDIV2)
 System core clock speed, 125 MHz unless board changes parameters.
 
#define CLOCK_USB    PLL_CLOCK(PLL_USB_VCO_FEEDBACK_SCALE, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2)
 USB clock speed.
 

Ranges for clock frequencies and clock settings

#define CLOCK_XOSC_MAX   MHZ(15)
 Maximum crystal frequency.
 
#define CLOCK_XOSC_MIN   MHZ(5)
 Minimum crystal frequency.
 
#define PLL_POSTDIV_MIN   (1U)
 Minimum value of the post PLL clock divers.
 
#define PLL_POSTDIV_MAX   (7U)
 Maximum value of the post PLL clock divers.
 
#define PLL_VCO_FEEDBACK_SCALE_MIN   (16U)
 Minimum value of the PLL VCO feedback scaler.
 
#define PLL_VCO_FEEDBACK_SCALE_MAX   (320U)
 Maximum value of the PLL VCO feedback scaler.
 
#define PLL_REF_DIV_MIN   (1U)
 Minimum value of the clock divider applied before feeding in the reference clock into the PLL.
 
#define PLL_REF_DIV_MAX   (1U)
 Minimum value of the clock divider applied before feeding in the reference clock into the PLL.
 
#define HAVE_GPIO_T
 Overwrite the default gpio_t type definition.
 
typedef uint32_t gpio_t
 
#define HAVE_GPIO_FLANK_T
 Override GPIO active flank values.
 
enum  gpio_flank_t {
  GPIO_LEVEL_LOW = 0x1 , GPIO_LEVEL_HIGH = 0x2 , GPIO_FALLING = 0x4 , GPIO_RISING = 0x8 ,
  GPIO_BOTH = 0xc
}
 

GPIO pad configuration register defines and types

#define GPIO_PAD_REGISTER_RESET_VALUE   (0x00000056)
 Reset value of the GPIO pad configuration register.
 
enum  {
  DRIVE_STRENGTH_2MA , DRIVE_STRENGTH_4MA , DRIVE_STRENGTH_8MA , DRIVE_STRENGTH_12MA ,
  DRIVE_STRENGTH_NUMOF
}
 Possible drive strength values for gpio_pad_ctrl_t::drive_strength. More...
 

GPIO I/O configuration register defines and types

#define GPIO_IO_REGISTER_RESET_VALUE   (0x0000001f)
 Reset value of the GPIO I/O configuration register.
 
enum  gpio_function_select_t {
  FUNCTION_SELECT_SPI = 1 , FUNCTION_SELECT_UART = 2 , FUNCTION_SELECT_I2C = 3 , FUNCTION_SELECT_PWM = 4 ,
  FUNCTION_SELECT_SIO = 5 , FUNCTION_SELECT_PIO0 = 6 , FUNCTION_SELECT_PIO1 = 7 , FUNCTION_SELECT_CLOCK = 8 ,
  FUNCTION_SELECT_USB = 9 , FUNCTION_SELECT_NONE = 31
}
 Possible function values for gpio_io_ctrl_t::function_select. More...
 
enum  {
  OUTPUT_OVERRIDE_NORMAL , OUTPUT_OVERRIDE_INVERT , OUTPUT_OVERRIDE_LOW , OUTPUT_OVERRIDE_HIGH ,
  OUTPUT_OVERRIDE_NUMOF
}
 Possible function values for gpio_io_ctrl_t::output_override. More...
 
enum  {
  OUTPUT_ENABLE_OVERRIDE_NOMARL , OUTPUT_ENABLE_OVERRIDE_INVERT , OUTPUT_ENABLE_OVERRIDE_DISABLE , OUTPUT_ENABLE_OVERRIDE_ENABLE ,
  OUTPUT_ENABLE_OVERRIDE_NUMOF
}
 Possible function values for gpio_io_ctrl_t::output_enable_override. More...
 
enum  {
  INPUT_OVERRIDE_NOMARL , INPUT_OVERRIDE_INVERT , INPUT_OVERRIDE_LOW , INPUT_OVERRIDE_HIGH ,
  INPUT_OVERRIDE_NUMOF
}
 Possible function values for gpio_io_ctrl_t::input_override. More...
 
enum  {
  IRQ_OVERRIDE_NORMAL , IRQ_OVERRIDE_INVERT , IRQ_OVERRIDE_LOW , IRQ_OVERRIDE_HIGH ,
  IRQ_OVERRIDE_NUMOF
}
 Possible function values for gpio_io_ctrl_t::irq_override. More...
 
#define HAVE_SPI_CLK_T
 Override SPI clock speed values.
 
enum  {
  SPI_CLK_100KHZ = KHZ(100) , SPI_CLK_400KHZ = KHZ(400) , SPI_CLK_1MHZ = MHZ(1) , SPI_CLK_5MHZ = MHZ(5) ,
  SPI_CLK_10MHZ = MHZ(10)
}
 
typedef uint32_t spi_clk_t
 SPI clock type.
 

RP2040 clock configuration

void clock_sys_configure_source (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_SYS_CTRL_SRC_Enum source)
 Configure the system clock to run from the reference clock, which is the default on boot.
 
void clock_sys_configure_aux_source (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum aux)
 Configure the system clock to run from an auxiliary clock source, like PLL.
 
void clock_ref_configure_source (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_REF_CTRL_SRC_Enum source)
 Configure the reference clock to run from a clock source, which is either the ROSC or the XOSC.
 
void clock_ref_configure_aux_source (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_REF_CTRL_AUXSRC_Enum aux)
 Configure the reference clock to run from an auxiliary clock source, like PLL.
 
void clock_periph_configure (CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum aux)
 Configure the peripheral clock to run from a dedicated auxiliary clock source.
 
void clock_gpout0_configure (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum aux)
 Configure gpio21 as clock output pin.
 
void clock_gpout1_configure (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum aux)
 Configure gpio23 as clock output pin.
 
void clock_gpout2_configure (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum aux)
 Configure gpio24 as clock output pin.
 
void clock_gpout3_configure (uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum aux)
 Configure gpio25 as clock output pin.
 
void clock_adc_configure (CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum aux)
 Configure the ADC clock to run from a dedicated auxiliary clock source.
 

RP2040 PLL configuration

void pll_start_sys (uint8_t ref_div, uint16_t vco_feedback_scale, uint8_t post_div_1, uint8_t post_div_2)
 Start the PLL for the system clock output[MHz] = f_ref / ref_div * vco_feedback_scale / post_div_1 / post_div_2.
 
void pll_start_usb (uint8_t ref_div, uint16_t vco_feedback_scale, uint8_t post_div_1, uint8_t post_div_2)
 Start the PLL for the USB clock output[MHz] = f_ref / ref_div * vco_feedback_scale / post_div_1 / post_div_2.
 
void pll_stop_sys (void)
 Stop the PLL of the system clock.
 
void pll_stop_usb (void)
 Stop the PLL of the USB clock.
 
void pll_reset_sys (void)
 Reset the PLL of the system clock.
 
void pll_reset_usb (void)
 Reset the PLL of the USB clock.
 

RP2040 XOSC configuration

void xosc_start (uint32_t f_ref)
 Configures the Crystal to run.
 
void xosc_stop (void)
 Stop the crystal.
 

RP2040 ROSC configuration

void rosc_start (void)
 Start the ring oscillator in default mode.
 
void rosc_stop (void)
 Turn off the ROSC to save power.
 

Macro Definition Documentation

◆ CLOCK_CORECLOCK

System core clock speed, 125 MHz unless board changes parameters.

Definition at line 122 of file periph_cpu.h.

◆ CLOCK_PERIPH

#define CLOCK_PERIPH   CLOCK_CORECLOCK

Peripheral clock (by default source from system clock)

Definition at line 200 of file periph_cpu.h.

◆ CLOCK_PERIPH_SOURCE

#define CLOCK_PERIPH_SOURCE   CLOCKS_CLK_PERI_CTRL_AUXSRC_clk_sys

How to source the peripheral clock (default: 125 MHz system clock)

Definition at line 193 of file periph_cpu.h.

◆ CLOCK_USB

USB clock speed.

Definition at line 128 of file periph_cpu.h.

◆ CLOCK_XOSC

#define CLOCK_XOSC   MHZ(12)

The RP2040 reference design attaches a 12 MHz crystal to the MCU, so we take this value as default.

Definition at line 110 of file periph_cpu.h.

◆ CLOCK_XOSC_MAX

#define CLOCK_XOSC_MAX   MHZ(15)

Maximum crystal frequency.

Definition at line 135 of file periph_cpu.h.

◆ CLOCK_XOSC_MIN

#define CLOCK_XOSC_MIN   MHZ(5)

Minimum crystal frequency.

Definition at line 136 of file periph_cpu.h.

◆ GPIO_IO_REGISTER_RESET_VALUE

#define GPIO_IO_REGISTER_RESET_VALUE   (0x0000001f)

Reset value of the GPIO I/O configuration register.

Definition at line 310 of file periph_cpu.h.

◆ GPIO_PAD_REGISTER_RESET_VALUE

#define GPIO_PAD_REGISTER_RESET_VALUE   (0x00000056)

Reset value of the GPIO pad configuration register.

Definition at line 275 of file periph_cpu.h.

◆ GPIO_PIN

#define GPIO_PIN (   port,
  pin 
)    ((((port) & 0)) | (pin))

Convert (port, pin) tuple to a gpio_t value.

Note
The RPX0XX MCU family only has a single GPIO port. Still the API requires a port parameter, which is currently ignored.

Definition at line 239 of file periph_cpu.h.

◆ GPIO_UNDEF

#define GPIO_UNDEF   UINT32_MAX

Definition of a fitting UNDEF value.

Definition at line 252 of file periph_cpu.h.

◆ HAVE_GPIO_FLANK_T

#define HAVE_GPIO_FLANK_T

Override GPIO active flank values.

Definition at line 258 of file periph_cpu.h.

◆ HAVE_GPIO_T

#define HAVE_GPIO_T

Overwrite the default gpio_t type definition.

Definition at line 245 of file periph_cpu.h.

◆ HAVE_SPI_CLK_T

#define HAVE_SPI_CLK_T

Override SPI clock speed values.

Definition at line 786 of file periph_cpu.h.

◆ PERIPH_SPI_NEEDS_TRANSFER_BYTE

#define PERIPH_SPI_NEEDS_TRANSFER_BYTE

Definition at line 813 of file periph_cpu.h.

◆ PERIPH_SPI_NEEDS_TRANSFER_REG

#define PERIPH_SPI_NEEDS_TRANSFER_REG

Definition at line 811 of file periph_cpu.h.

◆ PERIPH_SPI_NEEDS_TRANSFER_REGS

#define PERIPH_SPI_NEEDS_TRANSFER_REGS

Definition at line 812 of file periph_cpu.h.

◆ PERIPH_TIMER_PROVIDES_SET

#define PERIPH_TIMER_PROVIDES_SET

Prevent shared timer functions from being used.

Definition at line 443 of file periph_cpu.h.

◆ PLL_CLOCK

#define PLL_CLOCK (   vco_feedback,
  postdiv1,
  postdiv2 
)     (CLOCK_XOSC * (vco_feedback) / (postdiv1) / (postdiv2))

Calculate the resulting PLL clock frequency for the given parameters.

Definition at line 116 of file periph_cpu.h.

◆ PLL_POSTDIV_MAX

#define PLL_POSTDIV_MAX   (7U)

Maximum value of the post PLL clock divers.

Definition at line 138 of file periph_cpu.h.

◆ PLL_POSTDIV_MIN

#define PLL_POSTDIV_MIN   (1U)

Minimum value of the post PLL clock divers.

Definition at line 137 of file periph_cpu.h.

◆ PLL_REF_DIV_MAX

#define PLL_REF_DIV_MAX   (1U)

Minimum value of the clock divider applied before feeding in the reference clock into the PLL.

Definition at line 144 of file periph_cpu.h.

◆ PLL_REF_DIV_MIN

#define PLL_REF_DIV_MIN   (1U)

Minimum value of the clock divider applied before feeding in the reference clock into the PLL.

Definition at line 142 of file periph_cpu.h.

◆ PLL_SYS_POSTDIV1

#define PLL_SYS_POSTDIV1   6

First post-PLL clock divider for system clock.

Note
Must be in rage 1..7

Definition at line 65 of file periph_cpu.h.

◆ PLL_SYS_POSTDIV2

#define PLL_SYS_POSTDIV2   2

Second post-PLL clock divider for system clock.

Note
Must be in rage 1..7

Definition at line 74 of file periph_cpu.h.

◆ PLL_SYS_REF_DIV

#define PLL_SYS_REF_DIV   1

For generating the system clock via PLL, the XOSC reference clock can be divided.

The datasheet says for the supported frequency range of the crystal, only a divider of 1 is reasonable.

Definition at line 39 of file periph_cpu.h.

◆ PLL_SYS_VCO_FEEDBACK_SCALE

#define PLL_SYS_VCO_FEEDBACK_SCALE   125

VCO feedback scale used for system clock.

Note
The result of PLL_SYS_VCO_FEEDBACK_SCALE * CLOCK_XOSC must be in the range of 400 MHz to 1600 MHz

Definition at line 56 of file periph_cpu.h.

◆ PLL_USB_POSTDIV1

#define PLL_USB_POSTDIV1   5

First post-PLL clock divider for USB clock.

Note
Must be in rage 1..7

Definition at line 93 of file periph_cpu.h.

◆ PLL_USB_POSTDIV2

#define PLL_USB_POSTDIV2   2

Second post-PLL clock divider for USB clock.

Note
Must be in rage 1..7

Definition at line 102 of file periph_cpu.h.

◆ PLL_USB_REF_DIV

#define PLL_USB_REF_DIV   1

Same as PLL_SYS_REF_DIV but for the PLL generating the USB clock.

Definition at line 46 of file periph_cpu.h.

◆ PLL_USB_VCO_FEEDBACK_SCALE

#define PLL_USB_VCO_FEEDBACK_SCALE   40

VCO feedback scale used for USB clock.

Note
The result of PLL_USB_VCO_FEEDBACK_SCALE * CLOCK_XOSC must be in the range of 400 MHz to 1600 MHz

Definition at line 84 of file periph_cpu.h.

◆ PLL_VCO_FEEDBACK_SCALE_MAX

#define PLL_VCO_FEEDBACK_SCALE_MAX   (320U)

Maximum value of the PLL VCO feedback scaler.

Definition at line 140 of file periph_cpu.h.

◆ PLL_VCO_FEEDBACK_SCALE_MIN

#define PLL_VCO_FEEDBACK_SCALE_MIN   (16U)

Minimum value of the PLL VCO feedback scaler.

Definition at line 139 of file periph_cpu.h.

◆ PWM_CHANNEL_NUMOF

#define PWM_CHANNEL_NUMOF   (2)

Number of channels available per slice.

Definition at line 410 of file periph_cpu.h.

◆ PWM_SLICE_NUMOF

#define PWM_SLICE_NUMOF   (8)

Number of slices available per PWM device.

Definition at line 405 of file periph_cpu.h.

◆ RESETS_RESET_MASK

#define RESETS_RESET_MASK
Value:
(RESETS_RESET_usbctrl_Msk | \
RESETS_RESET_uart1_Msk | \
RESETS_RESET_uart0_Msk | \
RESETS_RESET_timer_Msk | \
RESETS_RESET_tbman_Msk | \
RESETS_RESET_sysinfo_Msk | \
RESETS_RESET_syscfg_Msk | \
RESETS_RESET_spi1_Msk | \
RESETS_RESET_spi0_Msk | \
RESETS_RESET_rtc_Msk | \
RESETS_RESET_pwm_Msk | \
RESETS_RESET_pll_usb_Msk | \
RESETS_RESET_pll_sys_Msk | \
RESETS_RESET_pio1_Msk | \
RESETS_RESET_pio0_Msk | \
RESETS_RESET_pads_qspi_Msk | \
RESETS_RESET_pads_bank0_Msk | \
RESETS_RESET_jtag_Msk | \
RESETS_RESET_io_qspi_Msk | \
RESETS_RESET_io_bank0_Msk | \
RESETS_RESET_i2c1_Msk | \
RESETS_RESET_i2c0_Msk | \
RESETS_RESET_dma_Msk | \
RESETS_RESET_busctrl_Msk | \
RESETS_RESET_adc_Msk)

Periphery blocks that can be reset.

Definition at line 206 of file periph_cpu.h.

Typedef Documentation

◆ gpio_t

typedef uint32_t gpio_t

Definition at line 246 of file periph_cpu.h.

◆ spi_clk_t

typedef uint32_t spi_clk_t

SPI clock type.

Definition at line 798 of file periph_cpu.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Possible function values for gpio_io_ctrl_t::output_enable_override.

Enumerator
OUTPUT_ENABLE_OVERRIDE_NOMARL 

enable output as specified by connected peripheral

OUTPUT_ENABLE_OVERRIDE_INVERT 

invert output enable setting of peripheral

OUTPUT_ENABLE_OVERRIDE_DISABLE 

disable output, overriding peripheral signal

OUTPUT_ENABLE_OVERRIDE_ENABLE 

enable output, overriding peripheral signal

OUTPUT_ENABLE_OVERRIDE_NUMOF 

number of possible output enable override settings

Definition at line 347 of file periph_cpu.h.

◆ anonymous enum

anonymous enum

Possible function values for gpio_io_ctrl_t::input_override.

Enumerator
INPUT_OVERRIDE_NOMARL 

don't mess with peripheral input signal

INPUT_OVERRIDE_INVERT 

invert signal to connected peripheral

INPUT_OVERRIDE_LOW 

signal low to connected peripheral

INPUT_OVERRIDE_HIGH 

signal high to connected peripheral

INPUT_OVERRIDE_NUMOF 

number of possible input override settings

Definition at line 358 of file periph_cpu.h.

◆ anonymous enum

anonymous enum

Possible function values for gpio_io_ctrl_t::irq_override.

Enumerator
IRQ_OVERRIDE_NORMAL 

don't mess with IRQ signal

IRQ_OVERRIDE_INVERT 

invert IRQ signal

IRQ_OVERRIDE_LOW 

set IRQ signal to low

IRQ_OVERRIDE_HIGH 

set IRQ signal to high

IRQ_OVERRIDE_NUMOF 

number of possible IRQ override settings

Definition at line 369 of file periph_cpu.h.

◆ anonymous enum

anonymous enum
Enumerator
SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

Definition at line 787 of file periph_cpu.h.

◆ anonymous enum

anonymous enum

Possible drive strength values for gpio_pad_ctrl_t::drive_strength.

Enumerator
DRIVE_STRENGTH_2MA 

set driver strength to 2 mA

DRIVE_STRENGTH_4MA 

set driver strength to 4 mA

DRIVE_STRENGTH_8MA 

set driver strength to 8 mA

DRIVE_STRENGTH_12MA 

set driver strength to 12 mA

DRIVE_STRENGTH_NUMOF 

number of different drive strength options

Definition at line 279 of file periph_cpu.h.

◆ anonymous enum

anonymous enum

Possible function values for gpio_io_ctrl_t::output_override.

Enumerator
OUTPUT_OVERRIDE_NORMAL 

drive pin from connected peripheral

OUTPUT_OVERRIDE_INVERT 

drive pin from connected peripheral, but invert output

OUTPUT_OVERRIDE_LOW 

drive pin low, overriding peripheral signal

OUTPUT_OVERRIDE_HIGH 

drive pin high, overriding peripheral signal

OUTPUT_OVERRIDE_NUMOF 

number of possible output override settings

Definition at line 336 of file periph_cpu.h.

◆ gpio_flank_t

Enumerator
GPIO_LEVEL_LOW 

emit interrupt level-triggered on low input

GPIO_LEVEL_HIGH 

emit interrupt level-triggered on low input

GPIO_FALLING 

emit interrupt on falling flank

GPIO_RISING 

emit interrupt on rising flank

GPIO_BOTH 

emit interrupt on both flanks

Definition at line 259 of file periph_cpu.h.

◆ gpio_function_select_t

Possible function values for gpio_io_ctrl_t::function_select.

Enumerator
FUNCTION_SELECT_SPI 

connect pin to the SPI peripheral (MISO/MOSI/SCK depends on pin)

FUNCTION_SELECT_UART 

connect pin to the UART peripheral (TXD/RXD depends on pin)

FUNCTION_SELECT_I2C 

connect pin to the I2C peripheral (SCL/SDA depends on pin)

FUNCTION_SELECT_PWM 

connect pin to the timer for PWM (channel depends on pin)

FUNCTION_SELECT_SIO 

use pin as vanilla GPIO

FUNCTION_SELECT_PIO0 

connect pin to the first PIO peripheral

FUNCTION_SELECT_PIO1 

connect pin to the second PIO peripheral

FUNCTION_SELECT_CLOCK 

connect pin to the timer (depending on pin: external clock, clock output, or not supported)

FUNCTION_SELECT_USB 

connect pin to the USB peripheral (function depends on pin)

FUNCTION_SELECT_NONE 

Reset value, pin unconnected.

Definition at line 314 of file periph_cpu.h.

Function Documentation

◆ clock_adc_configure()

void clock_adc_configure ( CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum  aux)

Configure the ADC clock to run from a dedicated auxiliary clock source.

Parameters
auxAuxiliary clock source

◆ clock_gpout0_configure()

void clock_gpout0_configure ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum  aux 
)

Configure gpio21 as clock output pin.

Can be used as an external clock source for another circuit or to check the expected signal with a logic analyzer

Parameters
f_inInput frequency
f_outOutput frequency
auxAuxiliary clock source

◆ clock_gpout1_configure()

void clock_gpout1_configure ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum  aux 
)

Configure gpio23 as clock output pin.

Can be used as an external clock source for another circuit or to check the expected signal with a logic analyzer

Parameters
f_inInput frequency
f_outOutput frequency
auxAuxiliary clock source

◆ clock_gpout2_configure()

void clock_gpout2_configure ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum  aux 
)

Configure gpio24 as clock output pin.

Can be used as an external clock source for another circuit or to check the expected signal with a logic analyzer

Parameters
f_inInput frequency
f_outOutput frequency
auxAuxiliary clock source

◆ clock_gpout3_configure()

void clock_gpout3_configure ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum  aux 
)

Configure gpio25 as clock output pin.

Can be used as an external clock source for another circuit or to check the expected signal with a logic analyzer

Parameters
f_inInput frequency
f_outOutput frequency
auxAuxiliary clock source

◆ clock_periph_configure()

void clock_periph_configure ( CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum  aux)

Configure the peripheral clock to run from a dedicated auxiliary clock source.

Parameters
auxAuxiliary clock source

◆ clock_ref_configure_aux_source()

void clock_ref_configure_aux_source ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_REF_CTRL_AUXSRC_Enum  aux 
)

Configure the reference clock to run from an auxiliary clock source, like PLL.

Note
The auxiliary must have been configured beforehand
Parameters
f_inInput frequency of the auxiliary clock source
f_outOutput frequency of the reference clock
auxWhich auxiliary clock source to use

◆ clock_ref_configure_source()

void clock_ref_configure_source ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_REF_CTRL_SRC_Enum  source 
)

Configure the reference clock to run from a clock source, which is either the ROSC or the XOSC.

Note
Make sure that ROSC or XOSC are properly set up
Parameters
f_inInput frequency of the reference clock
f_outOutput frequency of the system clock
sourceClock source

◆ clock_sys_configure_aux_source()

void clock_sys_configure_aux_source ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum  aux 
)

Configure the system clock to run from an auxiliary clock source, like PLL.

Note
The auxiliary must have been configured beforehand
Parameters
f_inInput frequency of the auxiliary clock source
f_outOutput frequency of the system clock
auxWhich auxiliary clock source to use

◆ clock_sys_configure_source()

void clock_sys_configure_source ( uint32_t  f_in,
uint32_t  f_out,
CLOCKS_CLK_SYS_CTRL_SRC_Enum  source 
)

Configure the system clock to run from the reference clock, which is the default on boot.

Parameters
f_inInput frequency of the reference clock
f_outOutput frequency of the system clock
sourceClock source

◆ gpio_io_register()

static volatile uint32_t * gpio_io_register ( uint8_t  pin)
inlinestatic

Get the IO control register for the given GPIO pin as word.

Definition at line 505 of file periph_cpu.h.

◆ gpio_pad_register()

static volatile uint32_t * gpio_pad_register ( uint8_t  pin)
inlinestatic

Get the PAD control register for the given GPIO pin as word.

Note: Only perform 32-bit writes to I/O registers.

Definition at line 487 of file periph_cpu.h.

◆ gpio_reset_all_config()

static void gpio_reset_all_config ( uint8_t  pin)
inlinestatic

Restore the default I/O and PAD configuration of the given GPIO pin.

Definition at line 532 of file periph_cpu.h.

◆ gpio_set_function_select()

static void gpio_set_function_select ( uint8_t  pin,
gpio_function_select_t  funcsel 
)
inlinestatic

Set the function select subregister for the given pin to the given value.

Definition at line 523 of file periph_cpu.h.

◆ gpio_set_io_config()

static void gpio_set_io_config ( uint8_t  pin,
gpio_io_ctrl_t  config 
)
inlinestatic

Convenience function to set the I/O configuration of the given pin using the bit-field convenience type.

Definition at line 514 of file periph_cpu.h.

◆ gpio_set_pad_config()

static void gpio_set_pad_config ( uint8_t  pin,
gpio_pad_ctrl_t  config 
)
inlinestatic

Convenience function to set the pad configuration of the given pin using the bit-field convenience type.

Definition at line 496 of file periph_cpu.h.

◆ periph_reset()

static void periph_reset ( uint32_t  components)
inlinestatic

Reset hardware components.

Parameters
componentsbitmask of components to be reset,
See also
RESETS_RESET_MASK

Definition at line 544 of file periph_cpu.h.

◆ periph_reset_done()

static void periph_reset_done ( uint32_t  components)
inlinestatic

Waits until hardware components have been reset.

Parameters
componentsbitmask of components that must have reset,
See also
RESETS_RESET_MASK

Definition at line 555 of file periph_cpu.h.

◆ pll_start_sys()

void pll_start_sys ( uint8_t  ref_div,
uint16_t  vco_feedback_scale,
uint8_t  post_div_1,
uint8_t  post_div_2 
)

Start the PLL for the system clock output[MHz] = f_ref / ref_div * vco_feedback_scale / post_div_1 / post_div_2.

Note
Usual setting should be (12 MHz, 1, 125, 6, 2) to get a 125 MHz system clock signal
Parameters
ref_divInput clock divisor
vco_feedback_scaleVCO feedback scales
post_div_1Output post divider factor 1
post_div_2Output post divider factor 2

◆ pll_start_usb()

void pll_start_usb ( uint8_t  ref_div,
uint16_t  vco_feedback_scale,
uint8_t  post_div_1,
uint8_t  post_div_2 
)

Start the PLL for the USB clock output[MHz] = f_ref / ref_div * vco_feedback_scale / post_div_1 / post_div_2.

Note
Usual setting should be (12 MHz, 1, 40, 5, 2) to get a 48 MHz USB clock signal
Parameters
ref_divInput clock divisor
vco_feedback_scaleVCO feedback scales
post_div_1Output post divider factor 1
post_div_2Output post divider factor 2

◆ rosc_start()

void rosc_start ( void  )

Start the ring oscillator in default mode.

The ROSC is running at boot time but may be turned off to save power when switching to the accurate XOSC. The default ROSC provides an instable frequency of 1.8 MHz to 12 MHz.

◆ rosc_stop()

void rosc_stop ( void  )

Turn off the ROSC to save power.

The system clock must be switched to to another lock source before the ROSC is stopped, other wise the chip will be lock up.

◆ xosc_start()

void xosc_start ( uint32_t  f_ref)

Configures the Crystal to run.

Parameters
f_refDesired frequency in Hz
Precondition
1 MHz <= f_ref <= 15 MHz.

The reference hardware manual suggests to use a 12 MHz crystal.