Common code for TI cc26xx/cc13xx family. More...
Common code for TI cc26xx/cc13xx family.
The CC26xx/C13xx is a family of micro controllers fabricated by Texas Instruments for low-power communications, using protocols such as BLE, IEEE 802.15.4g-2012, and proprietary radio protocols.
These family of MCUs is divided in two generations, the cc26x0/cc13x0, and the cc26x2/cc13x2 family. The difference is that the later provides more ROM and RAM and improvements on various peripherals.
|CC26x0/CC13x0||20 K||128 K|
|CC26x2/CC13x2||80 K||352 K|
RIOT provides built-in support to flash the Customer Configuration on the CC26xx/CC13xx MCUs. It can be done through Kconfig using
It will open the Kconfig terminal configuration utility, you may see the
Update CCFG option, selecting it will include the default configuration that Texas Instruments provides from their own SDK. You may change any further options available through Kconfig.
Once configuration is saved you may compile a new binary and flash it onto the device.
Development kits from Texas Instruments come with an XDS110 on-board debug probe that provides programming, flashing and debugging capabilities.
It can either use proprietary Texas Instruments tools for programming, or OpenOCD.
OpenOCD is the default programmer and debugger. Hence, flashing can be done by navigating to the application directory and running:
OPENOCD_DEBUG_ADAPTERto a different debugger.
TI maintains an outdated fork of OpenOCD that contains patches and special handling that have not upstreamed yet. It can be build using:
Otherwise, usage is identical with the upstream version of OpenOCD.
By passing (or exporting)
PROGRAMMER=jlink J-Link can be used to flash the board. This requires a J-Link compatible programmer / debugger. Since the XDS110 that TI's development boards use is not compatible, an external programmer has to be used. The upside is that flashing appears to be reliable with that.
The TI's Code Composer Studio provides the necessary tools to use the debug features of the XDS110; Uniflash provides flashing tools. Both programs can be found here:
Before using the XDS110 with the latest CCS/Uniflash versions the firmware for it needs to be updated. Texas Instruments has a guide to correctly update it here.
In order to make use of the programming and debugging capabilities of the XDS110 some environment variable needs to be set:
That assumes you have CCS 9.3.0 (for the path name) and Uniflash 5.2.0, adjust accordingly.
After that you can flash using the RIOT
make flash command on your application or to debug you first start the debug server:
And then on another terminal you can run:
It will open GDB and connect to the debug server automatically.
PROGRAMMER=uniflashto change the default programmer.
|CC26xx/CC13xx Power management. |
|Implementation specific CPU configuration options. |
|CPU specific definitions for internal peripheral handling. |
|ARM Cortex-M specific CPU configuration. |
|CC26xx/CC13xx specific CPU configuration. More...|
|Force VDDR high setting, enables higher output power but also higher power consumption. More...|
|Enable GPRAM and use 8K VIMS RAM as GPRAM (instead of cache). More...|
|This configures the level need to enter the bootloader backdoor at boot time. |
|DIO (pin) number used to enter the bootloader backdoor at boot time. |
|Disable GPRAM. |
|Customer Configuration (CCFG) More...|
|The input frequency of the external clock and is written to |
|Selects the TCXO type. More...|
|Maximum TCXO startup time in units of 100us. More...|
|Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled. More...|
|Enable DC/DC dithering if alternate DC/DC setting is enabled. More...|
|Inductor peak current if alternate DC/DC setting is enabled. More...|
|Signed delta value for IBIAS_INIT. |
|Signed delta value for IBIAS_OFFSET. |
|Maximum XOSC startup time (worst case) in units of 100us. |
|Total size of the CCFG in bytes. |
|Reserved by Texas Instruments for future use. More...|
|Disable TCXO. More...|
|Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). More...|
|Disable XOSC override functionality. More...|
|Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one. More...|
|DC/DC during recharge in powerdown. More...|
|DC/DC in active mode. More...|
|Reserved for future use byte TI. More...|
|VDDS BOD level. More...|
|LF clock option. More...|
|VDDR_TRIM_SLEEP_DELTA temperature compensation. More...|
|Reserved for future use by TI. |
|External crystal frequency. More...|
|Enable modification (delta) to XOSC cap-array. More...|
|Reserved for future use by TI. |
|Modifies trimmed XOSC cap-array step value. More...|
|Represents the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF. More...|
|Bootloader enable. More...|
|Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field. More...|
|DIO number that is level checked if the boot loader backdoor is enabled by the SET_BL_CONFIG_BL_ENABLE setting. |
|Enables the boot loader backdoor. More...|
|Enable CPU DAP. More...|
|Enable PWRPROF TAP (PRCM on x0 CPUs). More...|
|Enable Test TAP. More...|
|#define CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH 0|
|#define CONFIG_CC26XX_CC13XX_GPRAM 0|
|#define CONFIG_CC26XX_CC13XX_UPDATE_CCFG 0|
|#define SET_BL_CONFIG_BL_ENABLE 0xFF|
|#define SET_BL_CONFIG_BL_LEVEL 0x1|
|#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0x00|
|#define SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5|
|#define SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5|
|#define SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00|
|#define SET_EXT_LF_CLK_DIO 0x01|
|#define SET_EXT_LF_CLK_RTC_INCREMENT 0x800000|
|#define SET_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0|
|#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x0|
|#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0x8|
Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled.
The VMIN voltage is defnied as follows:
Voltage = (28 + ALT_DCDC_VMIN) / 16
0 = 1.75 V 1 = 1.8125 V ... 8 = 2.25 V ... 14 = 2.625 V 15 = 2.6875 V
|#define SET_MODE_CONF_1_TCXO_MAX_START 0x7F|
|#define SET_MODE_CONF_1_TCXO_TYPE 0x01|
Selects the TCXO type.
0h = CMOS type. Internal common-mode bias will not be enabled. 1h = Clipped-sine type. Internal common-mode bias will be enabled when TCXO is used.
|#define SET_MODE_CONF_DCDC_ACTIVE 0x0|
|#define SET_MODE_CONF_DCDC_RECHARGE 0x0|
|#define SET_MODE_CONF_SCLK_LF_OPTION 0x2|
|#define SET_MODE_CONF_VDDR_CAP 0x3A|
Represents the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF.
This should take into account capacitor tolerance and voltage dependent capacitance variation. This bit affects the recharge period calculation when going into powerdown or standby.
|#define SET_MODE_CONF_VDDR_EXT_LOAD 0x0|
|#define SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF|
|#define SET_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1|
VDDR_TRIM_SLEEP_DELTA temperature compensation.
1h = VDDR_TRIM_SLEEP_DELTA is not temperature compensated. 0h = RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time standby mode is entered. This improves low-temperature RCOSC_LF frequency stability in standby mode.
When temperature compensation is performed, the delta is calculates this way:
Delta = max (delta, min(8, floor(62-temp)/8))
Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current temperature in degrees C.
|#define SET_MODE_CONF_VDDS_BOD_LEVEL 0x1|
|#define SET_MODE_CONF_XOSC_CAP_MOD 0x1|
|#define SET_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF|
|#define SET_MODE_CONF_XOSC_FREQ 0x2|
|#define SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0|
Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).
0h = GPRAM is enabled and hence CACHE disabled. 1h = GPRAM is disabled and instead CACHE is enabled (default).
Disable alternate DC/DC settings.
0h = Enable alternate DC/DC settings. 1h = Disable alternate DC/DC settings.
|#define SET_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1|
|#define SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1|