25#include "cpu_conf_common.h"
49#define CPU_DEFAULT_IRQ_PRIO (1U)
50#define CPU_IRQ_NUMOF IRQN_COUNT
51#define CPU_FLASH_BASE FLASH_BASE
62#ifndef CONFIG_CC26XX_CC13XX_UPDATE_CCFG
63#define CONFIG_CC26XX_CC13XX_UPDATE_CCFG 0
72#ifndef CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH
73#define CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH 0
84#ifndef CONFIG_CC26XX_CC13XX_GPRAM
85#define CONFIG_CC26XX_CC13XX_GPRAM 0
92#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_HIGH)
93#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1
94#elif IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_LOW)
95#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x0
98#ifndef CONFIG_CC26XX_CC13XX_BL_LEVEL
99#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1
106#ifndef CONFIG_CC26XX_CC13XX_BL_PIN
107#define CONFIG_CC26XX_CC13XX_BL_PIN 0xFF
111#if IS_ACTIVE(CONFIG_CPU_FAM_CC13XX)
113#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH)
114#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0xC
115#define SET_MODE_CONF_VDDR_EXT_LOAD 0x1
120#if !IS_ACTIVE(CONFIG_CC26XX_CC13XX_GPRAM)
121#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1
124#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_ROM_BOOTLOADER)
125#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0xC5
126#define SET_BL_CONFIG_BL_ENABLE 0xC5
128#if defined(CONFIG_CC26XX_CC13XX_BL_LEVEL)
129#define SET_BL_CONFIG_BL_LEVEL CONFIG_CC26XX_CC13XX_BL_LEVEL
132#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_PIN_EN)
133#define SET_BL_CONFIG_BL_PIN_NUMBER CONFIG_CC26XX_CC13XX_BL_PIN
139#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_DIS_GPRAM)
154#ifndef SET_EXT_LF_CLK_DIO
155#define SET_EXT_LF_CLK_DIO 0x01
170#ifndef SET_EXT_LF_CLK_RTC_INCREMENT
171#define SET_EXT_LF_CLK_RTC_INCREMENT 0x800000
174#if defined(CPU_VARIANT_X2) || defined(DOXYGEN)
185#ifndef SET_MODE_CONF_1_TCXO_TYPE
186#define SET_MODE_CONF_1_TCXO_TYPE 0x01
196#ifndef SET_MODE_CONF_1_TCXO_MAX_START
197#define SET_MODE_CONF_1_TCXO_MAX_START 0x7F
220#ifndef SET_MODE_CONF_1_ALT_DCDC_VMIN
221#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0x8
229#ifndef SET_MODE_CONF_1_ALT_DCDC_DITHER_EN
230#define SET_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0
240#ifndef SET_MODE_CONF_1_ALT_DCDC_IPEAK
241#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x0
247#ifndef SET_MODE_CONF_1_DELTA_IBIAS_INIT
248#define SET_MODE_CONF_1_DELTA_IBIAS_INIT 0x0
254#ifndef SET_MODE_CONF_1_DELTA_IBIAS_OFFSET
255#define SET_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0
261#ifndef SET_MODE_CONF_1_XOSC_MAX_START
262#define SET_MODE_CONF_1_XOSC_MAX_START 0x10
268#ifndef SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG
269#define SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058
275#ifndef SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS
276#define SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS \
277 (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m >> \
278 CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s)
286#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_TCXO
287#define SET_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1
298#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM
299#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0
311#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING
312#define SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0
324#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR
325#define SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1
338#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA
339#define SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF
347#ifndef SET_MODE_CONF_DCDC_RECHARGE
348#define SET_MODE_CONF_DCDC_RECHARGE 0x0
356#ifndef SET_MODE_CONF_DCDC_ACTIVE
357#define SET_MODE_CONF_DCDC_ACTIVE 0x0
364#ifndef SET_MODE_CONF_VDDR_EXT_LOAD
365#define SET_MODE_CONF_VDDR_EXT_LOAD 0x0
375#ifndef SET_MODE_CONF_VDDS_BOD_LEVEL
376#define SET_MODE_CONF_VDDS_BOD_LEVEL 0x1
387#ifndef SET_MODE_CONF_SCLK_LF_OPTION
388#define SET_MODE_CONF_SCLK_LF_OPTION 0x2
405#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_TC
406#define SET_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1
412#ifndef SET_MODE_CONF_RTC_COMP
413#define SET_MODE_CONF_RTC_COMP 0x1
424#ifndef SET_MODE_CONF_XOSC_FREQ
425#define SET_MODE_CONF_XOSC_FREQ 0x2
434#ifndef SET_MODE_CONF_XOSC_CAP_MOD
435#define SET_MODE_CONF_XOSC_CAP_MOD 0x1
441#ifndef SET_MODE_CONF_HF_COMP
442#define SET_MODE_CONF_HF_COMP 0x1
450#ifndef SET_MODE_CONF_XOSC_CAPARRAY_DELTA
451#define SET_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF
462#ifndef SET_MODE_CONF_VDDR_CAP
463#define SET_MODE_CONF_VDDR_CAP 0x3A
473#ifndef SET_BL_CONFIG_BOOTLOADER_ENABLE
474#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0x00
483#ifndef SET_BL_CONFIG_BL_LEVEL
484#define SET_BL_CONFIG_BL_LEVEL 0x1
491#ifndef SET_BL_CONFIG_BL_PIN_NUMBER
492#define SET_BL_CONFIG_BL_PIN_NUMBER 0xFF
500#ifndef SET_BL_CONFIG_BL_ENABLE
501#define SET_BL_CONFIG_BL_ENABLE 0xFF
509#ifndef SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE
510#define SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5
518#ifndef SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE
519#define SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5
527#ifndef SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE
528#define SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00
CC26xx, CC13xx definitions.
CC26xx/CC13xx MCU I/O register definitions.
CC26xx/CC13xx CCFG register definitions.
Driver for the cc26xx/cc13xx GPIO controller.
definitions for the CC26xx/CC13XX GPT modules
CC26xx/CC13xx ROM Hard-API.
CC26xx/CC13xx MCU I/O register definitions.
CC26xx/CC13xx MCU I/O register definitions.
CC26xx/CC13xx MCU I/O register definitions.
CC26xx/CC13xx UART interface.
CC26xx/CC13xx VIMS register definitions.
CC26xx/CC13xx WDT register definitions.
Common macros and compiler attributes/pragmas configuration.