cpu_conf_cc26xx_cc13xx.h
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1/*
2 * Copyright (C) 2016 Leon George
3 * Copyright (C) 2020 Locha Inc
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef CPU_CONF_CC26XX_CC13XX_H
22#define CPU_CONF_CC26XX_CC13XX_H
23
24#include "kernel_defines.h"
25
26#include "cpu_conf_common.h"
27
28#include "cc26xx_cc13xx.h"
29
30#include "cc26xx_cc13xx_adi.h"
31#include "cc26xx_cc13xx_ccfg.h"
32#include "cc26xx_cc13xx_gpio.h"
33#include "cc26xx_cc13xx_gpt.h"
34#include "cc26xx_cc13xx_hard_api.h"
35#include "cc26xx_cc13xx_i2c.h"
36#include "cc26xx_cc13xx_ioc.h"
37#include "cc26xx_cc13xx_rfc.h"
38#include "cc26xx_cc13xx_uart.h"
39#include "cc26xx_cc13xx_vims.h"
40#include "cc26xx_cc13xx_wdt.h"
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
50#define CPU_DEFAULT_IRQ_PRIO (1U)
51#define CPU_IRQ_NUMOF IRQN_COUNT
52#define CPU_FLASH_BASE FLASH_BASE
63#ifndef CONFIG_CC26XX_CC13XX_UPDATE_CCFG
64#define CONFIG_CC26XX_CC13XX_UPDATE_CCFG 0
65#endif
66
73#ifndef CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH
74#define CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH 0
75#endif
76
85#ifndef CONFIG_CC26XX_CC13XX_GPRAM
86#define CONFIG_CC26XX_CC13XX_GPRAM 0
87#endif
88
93#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_HIGH)
94#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1
95#elif IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_LEVEL_ACTIVE_LOW)
96#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x0
97#endif
98
99#ifndef CONFIG_CC26XX_CC13XX_BL_LEVEL
100#define CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1
101#endif
102
107#ifndef CONFIG_CC26XX_CC13XX_BL_PIN
108#define CONFIG_CC26XX_CC13XX_BL_PIN 0xFF
109#endif
110
111/* high VDDR is available only on CC13xx CPUs */
112#if IS_ACTIVE(CONFIG_CPU_FAM_CC13XX)
113
114#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH)
115#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0xC
116#define SET_MODE_CONF_VDDR_EXT_LOAD 0x1
117#endif
118
119#endif /* IS_ACTIVE(CONFIG_CPU_FAM_CC13XX) */
120
121#if !IS_ACTIVE(CONFIG_CC26XX_CC13XX_GPRAM)
122#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1
123#endif
124
125#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_ROM_BOOTLOADER)
126#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0xC5
127#define SET_BL_CONFIG_BL_ENABLE 0xC5
129#if defined(CONFIG_CC26XX_CC13XX_BL_LEVEL)
130#define SET_BL_CONFIG_BL_LEVEL CONFIG_CC26XX_CC13XX_BL_LEVEL
131#endif
132
133#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_BL_PIN_EN)
134#define SET_BL_CONFIG_BL_PIN_NUMBER CONFIG_CC26XX_CC13XX_BL_PIN
135#endif
136
137#endif /* IS_USED(CONFIG_CC26XX_CC13XX_ROM_BOOTLOADER) */
138
139/* when GPRAM is not disabled, use it as a backup RAM */
140#if IS_ACTIVE(CONFIG_CC26XX_CC13XX_DIS_GPRAM)
141#define NUM_HEAPS (1)
142#else
143#define NUM_HEAPS (2)
144#endif
155#ifndef SET_EXT_LF_CLK_DIO
156#define SET_EXT_LF_CLK_DIO 0x01
157#endif
158
171#ifndef SET_EXT_LF_CLK_RTC_INCREMENT
172#define SET_EXT_LF_CLK_RTC_INCREMENT 0x800000
173#endif
174
175#if defined(CPU_VARIANT_X2) || defined(DOXYGEN)
186#ifndef SET_MODE_CONF_1_TCXO_TYPE
187#define SET_MODE_CONF_1_TCXO_TYPE 0x01
188#endif
189
197#ifndef SET_MODE_CONF_1_TCXO_MAX_START
198#define SET_MODE_CONF_1_TCXO_MAX_START 0x7F
199#endif
200
201#endif /* defined(CPU_VARIANT_X2) || defined(DOXYGEN) */
202
221#ifndef SET_MODE_CONF_1_ALT_DCDC_VMIN
222#define SET_MODE_CONF_1_ALT_DCDC_VMIN 0x8
223#endif
224
230#ifndef SET_MODE_CONF_1_ALT_DCDC_DITHER_EN
231#define SET_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0
232#endif
233
241#ifndef SET_MODE_CONF_1_ALT_DCDC_IPEAK
242#define SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x0
243#endif
244
248#ifndef SET_MODE_CONF_1_DELTA_IBIAS_INIT
249#define SET_MODE_CONF_1_DELTA_IBIAS_INIT 0x0
250#endif
251
255#ifndef SET_MODE_CONF_1_DELTA_IBIAS_OFFSET
256#define SET_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0
257#endif
258
262#ifndef SET_MODE_CONF_1_XOSC_MAX_START
263#define SET_MODE_CONF_1_XOSC_MAX_START 0x10
264#endif
265
269#ifndef SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG
270#define SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058
271#endif
272
276#ifndef SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS
277#define SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS \
278 (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_m >> \
279 CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_s)
280#endif
281
287#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_TCXO
288#define SET_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1
289#endif
290
299#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM
300#define SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0
301#endif
302
312#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING
313#define SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0
314#endif
315
325#ifndef SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR
326#define SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1
327#endif
328
339#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA
340#define SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF
341#endif
342
348#ifndef SET_MODE_CONF_DCDC_RECHARGE
349#define SET_MODE_CONF_DCDC_RECHARGE 0x0
350#endif
351
357#ifndef SET_MODE_CONF_DCDC_ACTIVE
358#define SET_MODE_CONF_DCDC_ACTIVE 0x0
359#endif
360
365#ifndef SET_MODE_CONF_VDDR_EXT_LOAD
366#define SET_MODE_CONF_VDDR_EXT_LOAD 0x0
367#endif
368
376#ifndef SET_MODE_CONF_VDDS_BOD_LEVEL
377#define SET_MODE_CONF_VDDS_BOD_LEVEL 0x1
378#endif
379
388#ifndef SET_MODE_CONF_SCLK_LF_OPTION
389#define SET_MODE_CONF_SCLK_LF_OPTION 0x2
390#endif
391
406#ifndef SET_MODE_CONF_VDDR_TRIM_SLEEP_TC
407#define SET_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1
408#endif
409
413#ifndef SET_MODE_CONF_RTC_COMP
414#define SET_MODE_CONF_RTC_COMP 0x1
415#endif
416
425#ifndef SET_MODE_CONF_XOSC_FREQ
426#define SET_MODE_CONF_XOSC_FREQ 0x2
427#endif
428
435#ifndef SET_MODE_CONF_XOSC_CAP_MOD
436#define SET_MODE_CONF_XOSC_CAP_MOD 0x1
437#endif
438
442#ifndef SET_MODE_CONF_HF_COMP
443#define SET_MODE_CONF_HF_COMP 0x1
444#endif
445
451#ifndef SET_MODE_CONF_XOSC_CAPARRAY_DELTA
452#define SET_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF
453#endif
454
463#ifndef SET_MODE_CONF_VDDR_CAP
464#define SET_MODE_CONF_VDDR_CAP 0x3A
465#endif
466
474#ifndef SET_BL_CONFIG_BOOTLOADER_ENABLE
475#define SET_BL_CONFIG_BOOTLOADER_ENABLE 0x00
476#endif
477
484#ifndef SET_BL_CONFIG_BL_LEVEL
485#define SET_BL_CONFIG_BL_LEVEL 0x1
486#endif
487
492#ifndef SET_BL_CONFIG_BL_PIN_NUMBER
493#define SET_BL_CONFIG_BL_PIN_NUMBER 0xFF
494#endif
495
501#ifndef SET_BL_CONFIG_BL_ENABLE
502#define SET_BL_CONFIG_BL_ENABLE 0xFF
503#endif
504
510#ifndef SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE
511#define SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5
512#endif
513
519#ifndef SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE
520#define SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5
521#endif
522
528#ifndef SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE
529#define SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00
530#endif
533#ifdef __cplusplus
534}
535#endif
536
537#endif /* CPU_CONF_CC26XX_CC13XX_H */
cc26xx_cc13xx.h
CC26xx, CC13xx definitions.
cc26xx_cc13xx_adi.h
CC26xx/CC13xx MCU I/O register definitions.
cc26xx_cc13xx_ccfg.h
CC26xx/CC13xx CCFG register definitions.
cc26xx_cc13xx_gpio.h
Driver for the cc26xx/cc13xx GPIO controller.
cc26xx_cc13xx_gpt.h
definitions for the CC26xx/CC13XX GPT modules
cc26xx_cc13xx_hard_api.h
CC26xx/CC13xx ROM Hard-API.
cc26xx_cc13xx_i2c.h
CC26xx/CC13xx MCU I/O register definitions.
cc26xx_cc13xx_ioc.h
CC26xx/CC13xx MCU I/O register definitions.
cc26xx_cc13xx_rfc.h
CC26xx/CC13xx MCU I/O register definitions.
cc26xx_cc13xx_uart.h
CC26xx/CC13xx UART interface.
cc26xx_cc13xx_vims.h
CC26xx/CC13xx VIMS register definitions.
cc26xx_cc13xx_wdt.h
CC26xx/CC13xx WDT register definitions.
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.