DMA CPU specific definitions for the STM32 family. More...

Detailed Description

DMA CPU specific definitions for the STM32 family.

Author: Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de; Vincent Dupont vince.nosp@m.nt@o.nosp@m.takey.nosp@m.s.co.nosp@m.m; Joshua DeWeese jdewe.nosp@m.ese@.nosp@m.prime.nosp@m.cont.nosp@m.rols..nosp@m.com

Definition in file cpu_dma.h.

This graph shows which files directly or indirectly include this file:

Data Structures
struct	dma_conf_t
	DMA configuration. More...

#define	DMA_CHAN_CONFIG_UNSUPPORTED (UINT8_MAX)
	DMA channel/trigger configuration for DMA peripherals without channel/trigger filtering such as the stm32f1 and stm32f3.

enum	dma_mode_t { DMA_PERIPH_TO_MEM = 0 , DMA_MEM_TO_PERIPH = 1 , DMA_MEM_TO_MEM = 2 }
	DMA modes. More...

enum	dma_burst_t { DMA_BURST_SINGLE = 0 , DMA_BURST_INCR4 = 1 , DMA_BURST_INCR8 = 2 , DMA_BURST_INCR16 = 3 }
	Burst Transfer modes for F2/F4/F7. More...

enum	dma_fifo_thresh_t { DMA_FIFO_FULL_1_4 = 0 , DMA_FIFO_FULL_1_2 = 1 , DMA_FIFO_FULL_3_4 = 2 , DMA_FIFO_FULL = 3 }
	Threshold selection in FIFO mode for F2/F4F7. More...

typedef unsigned	dma_t
	DMA type.

DMA Increment modes
#define	DMA_INC_SRC_ADDR (0x04)
	DMA increment source address.

#define	DMA_INC_DST_ADDR (0x08)
	DMA increment destination address.

#define	DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR \| DMA_INC_DST_ADDR)
	DMA increment source + destination address.

DMA data width
#define	DMA_DATA_WIDTH_BYTE (0x00)
	Byte width.

#define	DMA_DATA_WIDTH_HALF_WORD (0x01)
	Half word width (2 bytes)

#define	DMA_DATA_WIDTH_WORD (0x02)
	Word width (4 bytes)

Macro Definition Documentation

◆ DMA_CHAN_CONFIG_UNSUPPORTED

#define DMA_CHAN_CONFIG_UNSUPPORTED (UINT8_MAX)

DMA channel/trigger configuration for DMA peripherals without channel/trigger filtering such as the stm32f1 and stm32f3.

Definition at line 96 of file cpu_dma.h.

◆ DMA_DATA_WIDTH_BYTE

#define DMA_DATA_WIDTH_BYTE (0x00)

Byte width.

Definition at line 111 of file cpu_dma.h.

◆ DMA_DATA_WIDTH_HALF_WORD

#define DMA_DATA_WIDTH_HALF_WORD (0x01)

Half word width (2 bytes)

Definition at line 112 of file cpu_dma.h.

◆ DMA_DATA_WIDTH_WORD

#define DMA_DATA_WIDTH_WORD (0x02)

Word width (4 bytes)

Definition at line 113 of file cpu_dma.h.

◆ DMA_INC_BOTH_ADDR

#define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)

DMA increment source + destination address.

Definition at line 104 of file cpu_dma.h.

◆ DMA_INC_DST_ADDR

#define DMA_INC_DST_ADDR (0x08)

DMA increment destination address.

Definition at line 103 of file cpu_dma.h.

◆ DMA_INC_SRC_ADDR

#define DMA_INC_SRC_ADDR (0x04)

DMA increment source address.

Definition at line 102 of file cpu_dma.h.

Typedef Documentation

◆ dma_t

typedef unsigned dma_t

DMA type.

Definition at line 61 of file cpu_dma.h.

Enumeration Type Documentation

◆ dma_burst_t

enum dma_burst_t

Burst Transfer modes for F2/F4/F7.

Enumerator
DMA_BURST_SINGLE	single transfer
DMA_BURST_INCR4	incremental burst of 4 beats
DMA_BURST_INCR8	incremental burst of 8 beats
DMA_BURST_INCR16	incremental burst of 16 beats

Definition at line 75 of file cpu_dma.h.

◆ dma_fifo_thresh_t

enum dma_fifo_thresh_t

Threshold selection in FIFO mode for F2/F4F7.

Enumerator
DMA_FIFO_FULL_1_4	1/4 full FIFO
DMA_FIFO_FULL_1_2	1/2 full FIFO
DMA_FIFO_FULL_3_4	3/4 full FIFO
DMA_FIFO_FULL	Full FIFO.

Definition at line 85 of file cpu_dma.h.

◆ dma_mode_t

enum dma_mode_t

DMA modes.

Enumerator
DMA_PERIPH_TO_MEM	Peripheral to memory.
DMA_MEM_TO_PERIPH	Memory to peripheral.
DMA_MEM_TO_MEM	Memory to memory.

Definition at line 66 of file cpu_dma.h.