cfg_clock_default.h File Reference

Configure STM32G0/G4 clock. More...

Detailed Description

Configure STM32G0/G4 clock.

CORECLOCK cannot exceeds 64MHz core clock. LSE is 32768Hz. Default configuration use PLL clock as system clock. PLL input clock is HSI by default.

Author

Alexandre Abadie alexa.nosp@m.ndre.nosp@m..abad.nosp@m.ie@i.nosp@m.nria..nosp@m.fr

Definition in file cfg_clock_default.h.

#include "cfg_clock_common_fx_gx_mp1_c0.h"
#include "kernel_defines.h"
#include "macros/units.h"

Include dependency graph for cfg_clock_default.h:

Go to the source code of this file.

G0/G4 clock settings
#define	CLOCK_PLL_SRC   (CONFIG_CLOCK_HSI)
#define	CONFIG_CLOCK_PLL_M   (4)
#define	CONFIG_CLOCK_PLL_N   (85)
#define	CONFIG_CLOCK_PLL_R   (2)
#define	CLOCK_AHB   CLOCK_CORECLOCK /* max: 64MHz (G0), 170MHZ (G4) */
#define	CONFIG_CLOCK_APB1_DIV   (1)
#define	CLOCK_APB1   (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz (G0), 170MHZ (G4) */

Macro Definition Documentation

CLOCK_AHB

#define CLOCK_AHB   CLOCK_CORECLOCK /* max: 64MHz (G0), 170MHZ (G4) */

Definition at line 105 of file cfg_clock_default.h.

CLOCK_APB1

#define CLOCK_APB1   (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz (G0), 170MHZ (G4) */

Definition at line 110 of file cfg_clock_default.h.

CLOCK_PLL_SRC

#define CLOCK_PLL_SRC   (CONFIG_CLOCK_HSI)

Definition at line 52 of file cfg_clock_default.h.

CONFIG_CLOCK_APB1_DIV

#define CONFIG_CLOCK_APB1_DIV   (1)

Definition at line 108 of file cfg_clock_default.h.

CONFIG_CLOCK_PLL_M

#define CONFIG_CLOCK_PLL_M   (4)

Definition at line 60 of file cfg_clock_default.h.

CONFIG_CLOCK_PLL_N

#define CONFIG_CLOCK_PLL_N   (85)

Definition at line 67 of file cfg_clock_default.h.

CONFIG_CLOCK_PLL_R

#define CONFIG_CLOCK_PLL_R   (2)

Definition at line 74 of file cfg_clock_default.h.