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cpu_dma.h
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1/*
2 * Copyright (C) 2016 Freie Universität Berlin
3 * 2017 OTA keys S.A.
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
22#ifndef PERIPH_CPU_DMA_H
23#define PERIPH_CPU_DMA_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
32typedef struct {
55 int stream;
57
61typedef unsigned dma_t;
62
71
81
91
96#define DMA_CHAN_CONFIG_UNSUPPORTED (UINT8_MAX)
97
102#define DMA_INC_SRC_ADDR (0x04)
103#define DMA_INC_DST_ADDR (0x08)
104#define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
111#define DMA_DATA_WIDTH_BYTE (0x00)
112#define DMA_DATA_WIDTH_HALF_WORD (0x01)
113#define DMA_DATA_WIDTH_WORD (0x02)
116#ifdef MODULE_PERIPH_DMA
120#define DMA_STREAM_UNDEF (UINT_MAX)
121
125void dma_init(void);
126
143int dma_transfer(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
144 dma_mode_t mode, uint8_t flags);
145
151void dma_acquire(dma_t dma);
152
158void dma_release(dma_t dma);
159
168void dma_start(dma_t dma);
169
177uint16_t dma_suspend(dma_t dma);
178
185void dma_resume(dma_t dma, uint16_t remaining);
186
192void dma_stop(dma_t dma);
193
199void dma_wait(dma_t dma);
200
214int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
215 dma_mode_t mode, uint8_t flags);
216
231void dma_setup(dma_t dma, int chan, void *periph_addr, dma_mode_t mode,
232 uint8_t width, bool inc_periph);
233
254void dma_setup_ext(dma_t dma, dma_burst_t pburst, dma_burst_t mburst,
255 bool fifo, dma_fifo_thresh_t thresh, bool pfctrl);
256
265void dma_prepare(dma_t dma, void *mem, size_t len, bool incr_mem);
266
267#endif /* MODULE_PERIPH_DMA */
268
269#ifdef __cplusplus
270}
271#endif
272
273#endif /* PERIPH_CPU_DMA_H */
dma_burst_t
Burst Transfer modes for F2/F4/F7.
Definition cpu_dma.h:75
@ DMA_BURST_INCR4
incremental burst of 4 beats
Definition cpu_dma.h:77
@ DMA_BURST_INCR8
incremental burst of 8 beats
Definition cpu_dma.h:78
@ DMA_BURST_SINGLE
single transfer
Definition cpu_dma.h:76
@ DMA_BURST_INCR16
incremental burst of 16 beats
Definition cpu_dma.h:79
dma_fifo_thresh_t
Threshold selection in FIFO mode for F2/F4F7.
Definition cpu_dma.h:85
@ DMA_FIFO_FULL_3_4
3/4 full FIFO
Definition cpu_dma.h:88
@ DMA_FIFO_FULL_1_4
1/4 full FIFO
Definition cpu_dma.h:86
@ DMA_FIFO_FULL_1_2
1/2 full FIFO
Definition cpu_dma.h:87
@ DMA_FIFO_FULL
Full FIFO.
Definition cpu_dma.h:89
unsigned dma_t
DMA type.
Definition cpu_dma.h:61
dma_mode_t
DMA modes.
Definition cpu_dma.h:66
@ DMA_PERIPH_TO_MEM
Peripheral to memory.
Definition cpu_dma.h:67
@ DMA_MEM_TO_PERIPH
Memory to peripheral.
Definition cpu_dma.h:68
@ DMA_MEM_TO_MEM
Memory to memory.
Definition cpu_dma.h:69
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Prepare the DMA channel for an individual transfer.
void dma_init(void)
Initialize DMA.
void dma_wait(dma_t dma)
Wait for a DMA channel to finish the transfer.
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq)
Initialize a previously allocated DMA channel with one-time settings.
unsigned dma_t
DMA channel type.
void dma_start(dma_t dma)
Start a DMA transfer.
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55