Default clock configuration for STM32F0/F1/F3. More...

Detailed Description

Default clock configuration for STM32F0/F1/F3.

Author: Víctor Ariño victo.nosp@m.r.ar.nosp@m.ino@t.nosp@m.riag.nosp@m.nosys.nosp@m..com; Sören Tempel tempe.nosp@m.l@un.nosp@m.i-bre.nosp@m.men..nosp@m.de; Tristan Bruns tbrun.nosp@m.s@un.nosp@m.i-bre.nosp@m.men..nosp@m.de; Alexander Kurth kurth.nosp@m.1@un.nosp@m.i-bre.nosp@m.men..nosp@m.de; Alexandre Abadie alexa.nosp@m.ndre.nosp@m..abad.nosp@m.ie@i.nosp@m.nria..nosp@m.fr

#include "cfg_clock_common_fx_gx_mp1_c0.h"
#include "kernel_defines.h"
#include "macros/units.h"

Include dependency graph for cfg_clock_default.h:

F0/F1/F3 clock settings
#define	CONFIG_CLOCK_PLL_PREDIV (1)

#define	CONFIG_CLOCK_PLL_MUL (9)

#define	CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48MHz (F0), 72MHz (F1/F3)*/

#define	CONFIG_CLOCK_APB1_DIV (2)

#define	CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48MHz (F0), 36MHz (F1/F3)*/

#define	CONFIG_CLOCK_APB2_DIV (1)

#define	CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */

Macro Definition Documentation

#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48MHz (F0), 72MHz (F1/F3)*/

Definition at line 121 of file cfg_clock_default.h.

#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48MHz (F0), 36MHz (F1/F3)*/

Definition at line 130 of file cfg_clock_default.h.

#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */

Definition at line 140 of file cfg_clock_default.h.

#define CONFIG_CLOCK_APB1_DIV (2)

Definition at line 127 of file cfg_clock_default.h.

#define CONFIG_CLOCK_APB2_DIV (1)

Definition at line 138 of file cfg_clock_default.h.

#define CONFIG_CLOCK_PLL_MUL (9)

Definition at line 80 of file cfg_clock_default.h.

#define CONFIG_CLOCK_PLL_PREDIV (1)

Definition at line 64 of file cfg_clock_default.h.