NXP QN908x Serial Peripheral Interface (SPI)

NXP QN908x timer driver.

NXP QN908x timer driver.

Two of the FLEXCOMM interfaces in this chip can be used as SPI interfaces named SPI0 and SPI1, which correspond to FLEXCOMM2 and FLEXCOMM3. Note that FLEXCOMM2 (SPI0) is also shared with the I2C peripheral I2C1 and both can't be used at the same time.

The SPI flexcomm clock is directly driven from the AHB bus, so its clock is limited by the core CPU clock and the AHB divisor on the higher side with an optional frequency divider of up to 65536 to generate lower clock frequencies.

Multiple peripherals can be connected to the same SPI bus, using different CS pins, with a maximum of 4 hardware CS peripherals per bus and any number of software CS peripherals.

This driver uses the OSHA SPI Signal Names and while it only implements the Controller mode, the hardware is capable of operating in Peripheral mode as well so we use the COPI/CIPO names.

SPI configuration example (for periph_conf.h)

The following example uses only one hardware CS (number 0) and leaves the rest unused. Check the user manual for the full list of CS pins available.

When configuring the CS line on a driver, you should pass a SPI_HWCS to use the hardware CS mode defined in this configuration. To use any other GPIO as a CS line selected by software it is also possible to pass a GPIO_PIN pin.

static const spi_conf_t spi_config[] = {
.dev = SPI0,
.cipo_pin = GPIO_PIN(PORT_A, 5),
.copi_pin = GPIO_PIN(PORT_A, 4),
.clk_pin = GPIO_PIN(PORT_A, 30),
.cs_pin = {
GPIO_PIN(PORT_A, 3), /* Use as SPI_HWCS(0) */
port A
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338