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cpu_conf.h File Reference

Implementation specific CPU configuration options. More...

Detailed Description

Implementation specific CPU configuration options.

Author
iosabi iosab.nosp@m.i@pr.nosp@m.otonm.nosp@m.ail..nosp@m.com

Definition in file cpu_conf.h.

#include "cpu_conf_common.h"
#include "vendor/QN908XC.h"
#include "vendor/QN908XC_features.h"
+ Include dependency graph for cpu_conf.h:

Go to the source code of this file.

Macros

#define CONFIG_CPU_CLK_OSC32M_DIV   0
 Internal OSC32M clock input /2 divider enabled.
 
#define CONFIG_CPU_CLK_XTAL_DIV   0
 External XTAL 32 MHz clock input /2 divider enabled.
 
#define CONFIG_CPU_CLK_AHB_DIV   1u
 AHB clock divider.
 
#define CONFIG_CPU_CLK_APB_DIV   1u
 APB clock divider.
 
#define QN908X_CRP
 Default "Code Read Protection" allows everything.
 
#define CORTEXM_VECTOR_RESERVED_0X20   QN908X_CRP
 The "Code Read Protection" is stored at the offset 0x20.
 

ARM Cortex-M specific CPU configuration

#define CPU_DEFAULT_IRQ_PRIO   (1U)
 
#define CPU_IRQ_NUMOF   (NUMBER_OF_INT_VECTORS - 16)
 NUMBER_OF_INT_VECTORS in the QN908XC.h is defined as including the standard ARM interrupt vectors and headers, however CPU_IRQ_NUMOF does not include the first 15 interrupt values and the stack pointer.
 
#define CPU_FLASH_BASE   (QN908X_ROM_START_ADDR)
 The flash is aliased at several addresses in the memory range.
 
#define CPU_HAS_BITBAND   1
 Bit-Band configuration.
 

Clocks configuration

External and internal clocks configuration.

The QN908x has an internal 32 MHz RCO for the high frequency clock source and a 32 KHz RCO for the low frequency clock source, as well as external connections for a crystal oscillator (XTAL) of either 16 MHz or 32 MHz for the high frequency clock source and another connection for a 32.768 KHz XTAL for the low frequency clock normally used for accurate Bluetooth timing. Note that the "32 KHz" clock source is not exactly the same frequency whether you use the internal or external one.

#define CONFIG_BOARD_HAS_XTAL32K   0
 Whether the board has a 32.768 KHz crystal in XTAL32_IN / XTAL32_OUT.
 

32K low frequency clock selector

#define CONFIG_CPU_CLK_32K_XTAL
 Enabled when the 32K low frequency uses the external crystal.
 
#define CONFIG_CPU_CLK_32K_RCO
 Enabled when the 32K low frequency uses the internal oscillator.
 
#define CONFIG_BOARD_HAS_XTAL   0
 Whether the board has a 16 or 32 MHz crystal in XTAL_IN / XTAL_OUT.
 

External high frequency "XTAL" crystal frequency

#define CONFIG_CPU_CLK_XTAL_16M
 Enabled when the external XTAL is a 16 MHz one.
 
#define CONFIG_CPU_CLK_XTAL_32M
 Enabled when the external XTAL is a 32 MHz one.
 

System clock configuration selector

#define CONFIG_CPU_CLK_SYS_XTAL
 System clock is external crystal source (including divider).
 
#define CONFIG_CPU_CLK_SYS_OSC32M
 System clock is internal 32 MHz oscillator source (including divider).
 
#define CONFIG_CPU_CLK_SYS_32K
 System clock is the low frequency clock (32 or 32.768 KHz)
 

Code Read Protection

Image "Code Read Protection" field definitions.

The Code Read Protection (CRP) is a 32-bit field stored in one of the reserved fields in the Cortex-M interrupt vector and therefore part of the image. It allows to enable or disable access to the flash from the In-System Programming (ISP) interface to read, erase or write flash pages, as well as external SWD access for debugging or programming the flash. Not all the CRP values are valid and an invalid value may render the flash inaccessible and effectively brick the device.

To select the access level define the QN908X_CRP macro from the global compile options, otherwise the default value in this module will be used (allowing everything). The value of the uint32_t CRP field in the Image vector table should be the "or" of the following QN908X_CRP_* macros. Every field must be either enabled or disabled, otherwise it would result in an invalid CRP value.

#define QN908X_CRP_PROTECT_PAGES(X)   (255 - (X))
 Number of pages to protect (0 to 255).
 
#define QN908X_CRP_MASS_ERASE_ALLOW   (0x800)
 Mass erase from ISP allowed.
 
#define QN908X_CRP_MASS_ERASE_DISALLOW   (0x400)
 Mass erase from ISP not allowed.
 
#define QN908X_CRP_PAGE_ERASE_WRITE_ALLOW   (0x2000)
 Page erase/write from ISP (for unprotected pages) allowed.
 
#define QN908X_CRP_PAGE_ERASE_WRITE_DISALLOW   (0x1000)
 Page erase/write from ISP (for unprotected pages) not allowed.
 
#define QN908X_CRP_FLASH_READ_ALLOW   (0x8000)
 Flash read (for unprotected pages) from ISP allowed or not.
 
#define QN908X_CRP_FLASH_READ_DISALLOW   (0x4000)
 Flash read (for unprotected pages) from ISP not allowed.
 
#define QN908X_CRP_ISP_ENTRY_ALLOW   (0x20000)
 ISP entry is allowed (via CHIP_MODE pin).
 
#define QN908X_CRP_ISP_ENTRY_DISALLOW   (0x10000)
 ISP entry via CHIP_MODE pin is not allowed.
 
#define QN908X_CRP_EXTERNAL_ACCESS_ALLOW   (0x80000)
 External access is allowed (including SWD interface).
 
#define QN908X_CRP_EXTERNAL_ACCESS_DISALLOW   (0x40000)
 External access is not allowed (including SWD interface).
 

Macro Definition Documentation

◆ CONFIG_BOARD_HAS_XTAL

#define CONFIG_BOARD_HAS_XTAL   0

Whether the board has a 16 or 32 MHz crystal in XTAL_IN / XTAL_OUT.

Definition at line 107 of file cpu_conf.h.

◆ CONFIG_BOARD_HAS_XTAL32K

#define CONFIG_BOARD_HAS_XTAL32K   0

Whether the board has a 32.768 KHz crystal in XTAL32_IN / XTAL32_OUT.

Definition at line 74 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_32K_RCO

#define CONFIG_CPU_CLK_32K_RCO

Enabled when the 32K low frequency uses the internal oscillator.

Definition at line 89 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_32K_XTAL

#define CONFIG_CPU_CLK_32K_XTAL

Enabled when the 32K low frequency uses the external crystal.

Definition at line 85 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_AHB_DIV

#define CONFIG_CPU_CLK_AHB_DIV   1u

AHB clock divider.

The AHB clock is derived from the System clock using this divider value, between 1 and 8192, and serves as a clock source for ARM core, FSP, SCT, Quad-SPI, Flexcomm (UART, SPI, I2C), GPIO, BLE_AHB and DMA. Note: When BLE is enabled, the AHB clock must be at least the BLE clock (either 8 or 16 MHz) limiting the range of allowed values for this divider so that the AHB clock is 8, 16 or 32 MHz.

Definition at line 186 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_APB_DIV

#define CONFIG_CPU_CLK_APB_DIV   1u

APB clock divider.

The APB clock is derived from the AHB clock using this divide value, between 1 and 16, and serves as the clock source for several peripherals, such as the RTC, ADC, DAC, Capacitive Sense (CS) and optionally the WDT.

Definition at line 198 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_OSC32M_DIV

#define CONFIG_CPU_CLK_OSC32M_DIV   0

Internal OSC32M clock input /2 divider enabled.

Definition at line 135 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_SYS_32K

#define CONFIG_CPU_CLK_SYS_32K

System clock is the low frequency clock (32 or 32.768 KHz)

Definition at line 161 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_SYS_OSC32M

#define CONFIG_CPU_CLK_SYS_OSC32M

System clock is internal 32 MHz oscillator source (including divider).

Definition at line 157 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_SYS_XTAL

#define CONFIG_CPU_CLK_SYS_XTAL

System clock is external crystal source (including divider).

Definition at line 153 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_XTAL_16M

#define CONFIG_CPU_CLK_XTAL_16M

Enabled when the external XTAL is a 16 MHz one.

Definition at line 117 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_XTAL_32M

#define CONFIG_CPU_CLK_XTAL_32M

Enabled when the external XTAL is a 32 MHz one.

Definition at line 121 of file cpu_conf.h.

◆ CONFIG_CPU_CLK_XTAL_DIV

#define CONFIG_CPU_CLK_XTAL_DIV   0

External XTAL 32 MHz clock input /2 divider enabled.

Definition at line 142 of file cpu_conf.h.

◆ CORTEXM_VECTOR_RESERVED_0X20

#define CORTEXM_VECTOR_RESERVED_0X20   QN908X_CRP

The "Code Read Protection" is stored at the offset 0x20.

To modify the CRP field define the macro QN908X_CRP.

Definition at line 301 of file cpu_conf.h.

◆ CPU_DEFAULT_IRQ_PRIO

#define CPU_DEFAULT_IRQ_PRIO   (1U)

Definition at line 35 of file cpu_conf.h.

◆ CPU_FLASH_BASE

#define CPU_FLASH_BASE   (QN908X_ROM_START_ADDR)

The flash is aliased at several addresses in the memory range.

In particular, address 0 can be mapped to RAM or flash, so it is possible to run from address 0 from flash, or even turn off the flash altogether and run from RAM to save power. This setting uses the ROM_START_ADDR value set in the Makefile.

Definition at line 49 of file cpu_conf.h.

◆ CPU_HAS_BITBAND

#define CPU_HAS_BITBAND   1

Bit-Band configuration.

Definition at line 53 of file cpu_conf.h.

◆ CPU_IRQ_NUMOF

#define CPU_IRQ_NUMOF   (NUMBER_OF_INT_VECTORS - 16)

NUMBER_OF_INT_VECTORS in the QN908XC.h is defined as including the standard ARM interrupt vectors and headers, however CPU_IRQ_NUMOF does not include the first 15 interrupt values and the stack pointer.

Definition at line 41 of file cpu_conf.h.

◆ QN908X_CRP

#define QN908X_CRP
Value:
#define QN908X_CRP_ISP_ENTRY_ALLOW
ISP entry is allowed (via CHIP_MODE pin).
Definition cpu_conf.h:266
#define QN908X_CRP_PAGE_ERASE_WRITE_ALLOW
Page erase/write from ISP (for unprotected pages) allowed.
Definition cpu_conf.h:248
#define QN908X_CRP_EXTERNAL_ACCESS_ALLOW
External access is allowed (including SWD interface).
Definition cpu_conf.h:275
#define QN908X_CRP_PROTECT_PAGES(X)
Number of pages to protect (0 to 255).
Definition cpu_conf.h:234
#define QN908X_CRP_MASS_ERASE_ALLOW
Mass erase from ISP allowed.
Definition cpu_conf.h:239
#define QN908X_CRP_FLASH_READ_ALLOW
Flash read (for unprotected pages) from ISP allowed or not.
Definition cpu_conf.h:257

Default "Code Read Protection" allows everything.

Definition at line 287 of file cpu_conf.h.

◆ QN908X_CRP_EXTERNAL_ACCESS_ALLOW

#define QN908X_CRP_EXTERNAL_ACCESS_ALLOW   (0x80000)

External access is allowed (including SWD interface).

Definition at line 275 of file cpu_conf.h.

◆ QN908X_CRP_EXTERNAL_ACCESS_DISALLOW

#define QN908X_CRP_EXTERNAL_ACCESS_DISALLOW   (0x40000)

External access is not allowed (including SWD interface).

Definition at line 279 of file cpu_conf.h.

◆ QN908X_CRP_FLASH_READ_ALLOW

#define QN908X_CRP_FLASH_READ_ALLOW   (0x8000)

Flash read (for unprotected pages) from ISP allowed or not.

Definition at line 257 of file cpu_conf.h.

◆ QN908X_CRP_FLASH_READ_DISALLOW

#define QN908X_CRP_FLASH_READ_DISALLOW   (0x4000)

Flash read (for unprotected pages) from ISP not allowed.

Definition at line 261 of file cpu_conf.h.

◆ QN908X_CRP_ISP_ENTRY_ALLOW

#define QN908X_CRP_ISP_ENTRY_ALLOW   (0x20000)

ISP entry is allowed (via CHIP_MODE pin).

Definition at line 266 of file cpu_conf.h.

◆ QN908X_CRP_ISP_ENTRY_DISALLOW

#define QN908X_CRP_ISP_ENTRY_DISALLOW   (0x10000)

ISP entry via CHIP_MODE pin is not allowed.

Definition at line 270 of file cpu_conf.h.

◆ QN908X_CRP_MASS_ERASE_ALLOW

#define QN908X_CRP_MASS_ERASE_ALLOW   (0x800)

Mass erase from ISP allowed.

Definition at line 239 of file cpu_conf.h.

◆ QN908X_CRP_MASS_ERASE_DISALLOW

#define QN908X_CRP_MASS_ERASE_DISALLOW   (0x400)

Mass erase from ISP not allowed.

Definition at line 243 of file cpu_conf.h.

◆ QN908X_CRP_PAGE_ERASE_WRITE_ALLOW

#define QN908X_CRP_PAGE_ERASE_WRITE_ALLOW   (0x2000)

Page erase/write from ISP (for unprotected pages) allowed.

Definition at line 248 of file cpu_conf.h.

◆ QN908X_CRP_PAGE_ERASE_WRITE_DISALLOW

#define QN908X_CRP_PAGE_ERASE_WRITE_DISALLOW   (0x1000)

Page erase/write from ISP (for unprotected pages) not allowed.

Definition at line 252 of file cpu_conf.h.

◆ QN908X_CRP_PROTECT_PAGES

#define QN908X_CRP_PROTECT_PAGES (   X)    (255 - (X))

Number of pages to protect (0 to 255).

This defines the number of pages to protect starting from 0. A value of 0 in this macro means that no page is protected. The maximum number allowed to be passed to this macro is 255, however there are 256 pages in the flash. The last page is protected if any other page is protected.

Protected pages can't be erased or written to by the ISP.

Definition at line 234 of file cpu_conf.h.