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periph_cpu.h
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1/*
2 * SPDX-FileCopyrightText: 2015-2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017-2018 Eistec AB
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21#include <stdbool.h>
22
23#include "cpu.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#ifdef PORT_PCR_MUX
30# define KINETIS_HAVE_PCR
31#endif
32
33#ifdef SIM_PINSEL_REG
34# define KINETIS_HAVE_PINSEL
35#endif
36
37#ifdef ADC_CFG1_MODE_MASK
38# define KINETIS_HAVE_ADC_K
39#endif
40
41#ifdef SPI_CTAR_CPHA_MASK
42# define KINETIS_HAVE_MK_SPI
43#endif
44
45#ifdef LPTMR_CSR_TEN_MASK
46# define KINETIS_HAVE_LPTMR
47#endif
48
53#define HAVE_GPIO_T
54typedef uint16_t gpio_t;
56
60#define GPIO_UNDEF (0xffff)
61
65#define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
66
67#ifdef SIM_UIDH_UID_MASK
68/* Kinetis Cortex-M4 has a 128 bit SIM UID */
72#define CPUID_ADDR (&SIM->UIDH)
73
77#define CPUID_LEN (16U)
78#else /* defined(SIM_UIDH_UID_MASK) */
79/* Kinetis Cortex-M0+ has a 96 bit SIM UID */
83#define CPUID_ADDR (&SIM->UIDMH)
87#define CPUID_LEN (12U)
88#endif /* defined(SIM_UIDH_UID_MASK) */
89
99#define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
100
107#define SPI_HWCS(x) (x)
108
112#define SPI_HWCS_NUMOF (5)
113
117#define SPI_CS_UNDEF (GPIO_UNDEF)
118
119#ifndef DOXYGEN
124#define HAVE_SPI_CS_T
125typedef uint32_t spi_cs_t;
127#endif
128
133#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
134#define PERIPH_SPI_NEEDS_TRANSFER_REG 1
135#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
137
141#define PERIPH_TIMER_PROVIDES_SET
142
146#define TIMER_CHANNEL_NUMOF 1
147
152#define PM_NUM_MODES (4U)
153enum {
154 KINETIS_PM_LLS = 0,
155 KINETIS_PM_VLPS = 1,
156 KINETIS_PM_STOP = 2,
157 KINETIS_PM_WAIT = 3,
158};
159#if MODULE_PM_LAYERED
160#include "pm_layered.h"
164#define PM_BLOCK(x) pm_block(x)
168#define PM_UNBLOCK(x) pm_unblock(x)
169#else
170/* ignore these calls when not using pm_layered */
171#define PM_BLOCK(x)
172#define PM_UNBLOCK(x)
173#endif
175
176#ifndef DOXYGEN
181#define HAVE_GPIO_MODE_T
182typedef enum {
183 GPIO_IN = GPIO_MODE(0, 0, 0, 0),
184 GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
185 GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
186 GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
187 GPIO_OD = GPIO_MODE(1, 0, 1, 1),
188 GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
191#endif /* ndef DOXYGEN */
192
193#ifdef KINETIS_HAVE_PCR
199typedef enum {
200 GPIO_AF_ANALOG = PORT_PCR_MUX(0),
201 GPIO_AF_GPIO = PORT_PCR_MUX(1),
202 GPIO_AF_2 = PORT_PCR_MUX(2),
203 GPIO_AF_3 = PORT_PCR_MUX(3),
204 GPIO_AF_4 = PORT_PCR_MUX(4),
205 GPIO_AF_5 = PORT_PCR_MUX(5),
206 GPIO_AF_6 = PORT_PCR_MUX(6),
207 GPIO_AF_7 = PORT_PCR_MUX(7),
208#ifdef PORT_PCR_ODE_MASK
209 GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
210#endif
211 GPIO_PCR_PD = (PORT_PCR_PE_MASK),
212 GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
213} gpio_pcr_t;
214#endif /* KINETIS_HAVE_PCR */
215
216#ifndef DOXYGEN
221#ifdef KINETIS_HAVE_PCR
222#define HAVE_GPIO_FLANK_T
223typedef enum {
224 GPIO_RISING = PORT_PCR_IRQC(0x9),
225 GPIO_FALLING = PORT_PCR_IRQC(0xa),
226 GPIO_BOTH = PORT_PCR_IRQC(0xb),
228#endif /* KINETIS_HAVE_PCR */
230#endif /* ndef DOXYGEN */
231
237enum {
238 PORT_A = 0,
239 PORT_B = 1,
240 PORT_C = 2,
241 PORT_D = 3,
242 PORT_E = 4,
243 PORT_F = 5,
244 PORT_G = 6,
246};
247
248#ifndef DOXYGEN
253#define HAVE_ADC_RES_T
254#ifdef KINETIS_HAVE_ADC_K
255typedef enum {
256 ADC_RES_6BIT = (0xfe),
257 ADC_RES_8BIT = ADC_CFG1_MODE(0),
258 ADC_RES_10BIT = ADC_CFG1_MODE(2),
259 ADC_RES_12BIT = ADC_CFG1_MODE(1),
260 ADC_RES_14BIT = (0xff),
261 ADC_RES_16BIT = ADC_CFG1_MODE(3)
262} adc_res_t;
263#endif /* KINETIS_HAVE_ADC_K */
265
266#if defined(FTM_CnSC_MSB_MASK)
270#define PWM_CHAN_MAX (4U)
271
276#define HAVE_PWM_MODE_T
277typedef enum {
278 PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
279 PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
280 PWM_CENTER = (FTM_CnSC_MSB_MASK)
281} pwm_mode_t;
282#endif /* defined(FTM_CnSC_MSB_MASK) */
283#endif /* ndef DOXYGEN */
284
288typedef enum {
292#if defined(UART_C1_M_MASK) || DOXYGEN
293 /* LPUART and UART mode bits coincide, so the same setting for UART works on
294 * the LPUART as well */
295 UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
296#elif defined(LPUART_CTRL_M_MASK)
297 /* For CPUs which only have the LPUART */
298 UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
299#endif
301#if defined(UART_C1_M_MASK) || DOXYGEN
302 UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
303#elif defined(LPUART_CTRL_M_MASK)
304 /* For CPUs which only have the LPUART */
305 UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
306#endif
308
309#ifndef DOXYGEN
314
315#ifdef KINETIS_HAVE_MK_SPI
316#define HAVE_SPI_MODE_T
317typedef enum {
318#if defined(SPI_CTAR_CPHA_MASK)
319 SPI_MODE_0 = 0,
320 SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
321 SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
322 SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
323#elif defined(SPI_C1_CPHA_MASK)
324 SPI_MODE_0 = 0,
325 SPI_MODE_1 = (SPI_C1_CPHA_MASK),
326 SPI_MODE_2 = (SPI_C1_CPOL_MASK),
327 SPI_MODE_3 = (SPI_C1_CPOL_MASK | SPI_C1_CPHA_MASK)
328#endif
329} spi_mode_t;
331#endif /* KINETIS_HAVE_MK_SPI */
332#endif /* ndef DOXYGEN */
333
337typedef struct {
341 ADC_Type *dev;
347 gpio_t pin;
354 uint8_t chan;
360 uint8_t avg;
361} adc_conf_t;
362
366#define ADC_AVG_NONE (0)
370#define ADC_AVG_MAX (ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3))
371
372#if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
376typedef struct {
377 DAC_Type *dev;
378 volatile uint32_t *scgc_addr;
379 uint8_t scgc_bit;
380} dac_conf_t;
381#endif
382
386typedef struct {
390 uint8_t count_ch;
391} pit_conf_t;
392
393#ifdef KINETIS_HAVE_LPTMR
397typedef struct {
399 LPTMR_Type *dev;
401 uint32_t base_freq;
403 uint8_t src;
405 uint8_t irqn;
406} lptmr_conf_t;
407#endif /* KINETIS_HAVE_LPTMR */
408
409#ifdef FTM_CnSC_MSB_MASK
413typedef struct {
414 FTM_Type* ftm;
415 struct {
416 gpio_t pin;
417 uint8_t af;
418 uint8_t ftm_chan;
419 } chan[PWM_CHAN_MAX];
420 uint8_t chan_numof;
421 uint8_t ftm_num;
422#ifdef KINETIS_HAVE_PINSEL
423 volatile uint32_t *pinsel;
424 uint32_t pinsel_mask;
425 uint32_t pinsel_val;
426#endif
427} pwm_conf_t;
428#endif
429
430#ifndef DOXYGEN
431#define HAVE_I2C_SPEED_T
432typedef enum {
433 I2C_SPEED_LOW = 10000ul,
434 I2C_SPEED_NORMAL = 100000ul,
435 I2C_SPEED_FAST = 400000ul,
436 I2C_SPEED_FAST_PLUS = 1000000ul,
437 /* High speed is not supported without external hardware hacks */
438 I2C_SPEED_HIGH = 3400000ul,
444#define PERIPH_I2C_NEED_READ_REG
445#define PERIPH_I2C_NEED_READ_REGS
446#define PERIPH_I2C_NEED_WRITE_REG
447#define PERIPH_I2C_NEED_WRITE_REGS
449#endif /* !defined(DOXYGEN) */
450
454typedef struct {
455 I2C_Type *i2c;
456 gpio_t scl_pin;
457 gpio_t sda_pin;
458 uint32_t freq;
461 uint32_t scl_pcr;
462 uint32_t sda_pcr;
463} i2c_conf_t;
464
468typedef struct {
469 SPI_Type *dev;
470 gpio_t pin_miso;
471 gpio_t pin_mosi;
472 gpio_t pin_clk;
474#ifdef KINETIS_HAVE_PCR
475 gpio_pcr_t pcr;
476#endif /* KINETIS_HAVE_PCR */
477#ifdef KINETIS_HAVE_PINSEL
478 volatile uint32_t *pinsel;
479 uint32_t pinsel_mask;
480 uint32_t pinsel_val;
481#endif
482 uint32_t simmask;
483} spi_conf_t;
484
488enum {
490#ifdef KINETIS_HAVE_LPTMR
491 TIMER_LPTMR,
492#endif /* KINETIS_HAVE_LPTMR */
493};
494
500#define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
501#ifdef KINETIS_HAVE_LPTMR
503#define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
504#endif /* KINETIS_HAVE_LPTMR */
506
511#define RTT_DEV (TIMER_LPTMR_DEV(0))
512#define RTT_MAX_VALUE (0x0000ffff)
513#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
514#define RTT_MAX_FREQUENCY (32768U) /* in Hz */
515#define RTT_MIN_FREQUENCY (1U) /* in Hz */
516#ifndef RTT_FREQUENCY
517#define RTT_FREQUENCY RTT_MAX_FREQUENCY
518#endif
519#if IS_USED(MODULE_PERIPH_RTT)
520/* On kinetis periph_rtt is built on top on an LPTIMER so if used it
521 will conflict with xtimer, if a LPTIMER backend and RTT are needed
522 consider using ztimer */
523#define KINETIS_XTIMER_SOURCE_PIT 1
524#endif
525/* When setting a new compare value, the value must be at least 5 more
526 than the current sleep timer value. Otherwise, the timer compare
527 event may be lost. */
529
537
541typedef struct {
542 void *dev;
543 uint32_t freq;
544 gpio_t pin_rx;
545 gpio_t pin_tx;
546#ifdef KINETIS_HAVE_PCR
547 uint32_t pcr_rx;
548 uint32_t pcr_tx;
549#endif
550#ifdef KINETIS_HAVE_PINSEL
551 volatile uint32_t *pinsel;
552 uint32_t pinsel_mask;
553 uint32_t pinsel_val;
554#endif
556 volatile uint32_t *scgc_addr;
557 uint8_t scgc_bit;
561
562#if !defined(KINETIS_HAVE_PLL) && defined(MODULE_PERIPH_MCG) \
563 && defined(MCG_C6_PLLS_MASK) || DOXYGEN
567#define KINETIS_HAVE_PLL 1
568#else
569#define KINETIS_HAVE_PLL 0
570#endif
571
572#ifdef MODULE_PERIPH_MCG_LITE
576typedef enum kinetis_mcg_mode {
577 KINETIS_MCG_MODE_LIRC8M = 0,
578 KINETIS_MCG_MODE_HIRC = 1,
579 KINETIS_MCG_MODE_EXT = 2,
580 KINETIS_MCG_MODE_LIRC2M = 3,
581 KINETIS_MCG_MODE_NUMOF,
582} kinetis_mcg_mode_t;
583#endif /* MODULE_PERIPH_MCG_LITE */
584
585#ifdef MODULE_PERIPH_MCG
589typedef enum kinetis_mcg_mode {
590 KINETIS_MCG_MODE_FEI = 0,
591 KINETIS_MCG_MODE_FEE = 1,
592 KINETIS_MCG_MODE_FBI = 2,
593 KINETIS_MCG_MODE_FBE = 3,
594 KINETIS_MCG_MODE_BLPI = 4,
595 KINETIS_MCG_MODE_BLPE = 5,
596#if KINETIS_HAVE_PLL
597 KINETIS_MCG_MODE_PBE = 6,
598 KINETIS_MCG_MODE_PEE = 7,
599#endif
600 KINETIS_MCG_MODE_NUMOF,
601} kinetis_mcg_mode_t;
602
606typedef enum {
608 KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
610 KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
612 KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
614 KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
616 KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
618 KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
620 KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
622 KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
623} kinetis_mcg_fll_t;
624
625#endif /* MODULE_PERIPH_MCG */
626#if defined(MODULE_PERIPH_MCG) || defined(MODULE_PERIPH_MCG_LITE)
627
631typedef enum {
632 KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
633 KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
634 KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
635} kinetis_mcg_erc_range_t;
636
643typedef enum {
652 KINETIS_CLOCK_OSC0_EN = (1 << 0),
661 KINETIS_CLOCK_RTCOSC_EN = (1 << 1),
678 KINETIS_CLOCK_USE_FAST_IRC = (1 << 2),
687 KINETIS_CLOCK_MCGIRCLK_EN = (1 << 3),
698 KINETIS_CLOCK_MCGIRCLK_STOP_EN = (1 << 4),
709 KINETIS_CLOCK_MCGPCLK_EN = (1 << 5),
710} kinetis_clock_flags_t;
711
715typedef struct {
725 uint32_t clkdiv1;
737 uint32_t rtc_clc;
751 uint32_t osc32ksel;
757 unsigned int clock_flags;
763 kinetis_mcg_mode_t default_mode;
769 kinetis_mcg_erc_range_t erc_range;
780 uint8_t osc_clc;
781#ifdef MODULE_PERIPH_MCG
791 uint8_t oscsel;
792#endif /* MODULE_PERIPH_MCG */
804 uint8_t fcrdiv;
805#ifdef MODULE_PERIPH_MCG_LITE
817 uint8_t lirc_div2;
818#else
828 uint8_t fll_frdiv;
835 kinetis_mcg_fll_t fll_factor_fei;
842 kinetis_mcg_fll_t fll_factor_fee;
843#if KINETIS_HAVE_PLL
853 uint8_t pll_prdiv;
863 uint8_t pll_vdiv;
864#endif /* KINETIS_HAVE_PLL */
865#endif /* MODULE_PERIPH_MCG */
866} clock_config_t;
867#endif /* MODULE_PERIPH_MCG || MODULE_PERIPH_MCG_LITE */
874void gpio_init_port(gpio_t pin, uint32_t pcr);
875
876#ifdef __cplusplus
877}
878#endif
879
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_G
port G
Definition periph_cpu.h:49
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_F
port F
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:43
@ PORT_D
port D
Definition periph_cpu.h:46
gpio_flank_t
Definition periph_cpu.h:176
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:161
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:160
i2c_speed_t
Definition periph_cpu.h:272
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition periph_cpu.h:276
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition periph_cpu.h:273
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition periph_cpu.h:278
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:275
pwm_mode_t
@ PWM_CENTER
center aligned
@ PWM_LEFT
left aligned
@ PWM_RIGHT
right aligned
#define PWM_CHAN_MAX
PWM configuration structure.
uart_type_t
UART hardware module types.
Definition cpu_uart.h:33
#define GPIO_MODE(x, y)
Internal macro for combining pin mode (x) and pull-up/down (y).
Definition periph_cpu.h:147
enum IRQn IRQn_Type
Interrupt Number Definition.
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:88
adc_res_t
Possible ADC resolution settings.
Definition adc.h:92
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition adc.h:98
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:94
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:97
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:93
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:95
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:96
gpio_t spi_cs_t
Chip select pin type overlaps with gpio_t so it can be casted to this.
Definition spi.h:135
@ TIMER_PIT
PIT.
Definition periph_cpu.h:489
uart_type_t
UART hardware module types.
Definition periph_cpu.h:533
@ KINETIS_LPUART
Kinetis Low-power UART (LPUART) module type.
Definition periph_cpu.h:535
@ KINETIS_UART
Kinetis UART module type.
Definition periph_cpu.h:534
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
uart_mode_t
UART transmission modes.
Definition periph_cpu.h:288
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition periph_cpu.h:290
@ UART_MODE_8E1
8 data bits, even parity, 1 stop bit
Definition periph_cpu.h:295
@ UART_MODE_8O1
8 data bits, odd parity, 1 stop bit
Definition periph_cpu.h:302
@ GPIO_PORTS_NUMOF
overall number of available ports
Definition periph_cpu.h:245
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
Definition periph_cpu.h:112
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:39
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:40
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:42
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:41
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:43
Layered low power mode infrastructure.
ADC device configuration.
Definition periph_cpu.h:374
uint8_t avg
Hardware averaging configuration.
Definition periph_cpu.h:360
ADC_TypeDef * dev
ADC device used.
Definition periph_cpu.h:375
gpio_t pin
pin connected to the channel
Definition periph_cpu.h:284
uint8_t chan
CPU ADC channel connected to the pin.
Definition periph_cpu.h:286
DAC line configuration data.
Definition periph_cpu.h:297
I2C configuration structure.
Definition periph_cpu.h:295
i2c_speed_t speed
Configured bus speed, actual speed may be lower but never higher.
Definition periph_cpu.h:300
uint32_t freq
I2C module clock frequency, usually CLOCK_BUSCLOCK or CLOCK_CORECLOCK.
Definition periph_cpu.h:458
IRQn_Type irqn
I2C event interrupt number.
Definition periph_cpu.h:459
I2C_Type * i2c
Pointer to hardware module registers.
Definition periph_cpu.h:455
uint32_t sda_pcr
PORT module PCR setting for the SDA pin.
Definition periph_cpu.h:462
gpio_t sda_pin
SDA GPIO pin.
Definition periph_cpu.h:298
gpio_t scl_pin
SCL GPIO pin.
Definition periph_cpu.h:299
uint32_t scl_pcr
PORT module PCR setting for the SCL pin.
Definition periph_cpu.h:461
CPU specific timer PIT module configuration.
Definition periph_cpu.h:386
uint8_t prescaler_ch
Prescaler channel.
Definition periph_cpu.h:388
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
Definition periph_cpu.h:390
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
gpio_t pin_clk
CLK pin used.
Definition periph_cpu.h:472
spi_cs_t pin_cs[SPI_HWCS_NUMOF]
pins used for HW cs lines
Definition periph_cpu.h:473
gpio_t pin_mosi
MOSI pin used.
Definition periph_cpu.h:471
gpio_t pin_miso
MISO pin used.
Definition periph_cpu.h:470
uint32_t simmask
bit in the SIM register
Definition periph_cpu.h:482
UART device configuration.
Definition periph_cpu.h:214
uint8_t pinsel
PINSEL# of the RX and TX pin.
Definition periph_cpu.h:81
uart_type_t type
Hardware module type (KINETIS_UART or KINETIS_LPUART)
Definition periph_cpu.h:559
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.
Definition periph_cpu.h:544
uint8_t irqn
IRQ channel.
Definition periph_cpu.h:332
gpio_t pin_tx
TX pin.
Definition periph_cpu.h:545
uint8_t scgc_bit
Clock enable bit, within the register.
Definition periph_cpu.h:557
uart_mode_t mode
UART mode: data bits, parity, stop bits.
Definition periph_cpu.h:558
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
Definition periph_cpu.h:556
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
Definition periph_cpu.h:543