21#include "periph_cpu.h"
32static const clock_config_t clock_config = {
41 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
42 SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
44 .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
47 KINETIS_CLOCK_RTCOSC_EN |
48 KINETIS_CLOCK_USE_FAST_IRC |
50 .default_mode = KINETIS_MCG_MODE_PEE,
52 .erc_range = KINETIS_MCG_ERC_RANGE_VERY_HIGH,
54 .oscsel = MCG_C7_OSCSEL(0),
55 .fcrdiv = MCG_SC_FCRDIV(0),
56 .fll_frdiv = MCG_C1_FRDIV(0b111),
57 .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464,
58 .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920,
59 .pll_prdiv = MCG_C5_PRDIV0(0b10011),
60 .pll_vdiv = MCG_C6_VDIV0(0b00000),
62#define CLOCK_CORECLOCK (60000000ul)
63#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
81#define LPTMR_NUMOF (1U)
82#define LPTMR_CONFIG { \
85 .irqn = LPTMR0_IRQn, \
87 .base_freq = 32768u, \
90#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
92#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
93#define PIT_ISR_0 isr_pit1
94#define PIT_ISR_1 isr_pit3
95#define LPTMR_ISR_0 isr_lptmr0
108 .pcr_rx = PORT_PCR_MUX(3),
109 .pcr_tx = PORT_PCR_MUX(3),
110 .irqn = UART0_RX_TX_IRQn,
111 .scgc_addr = &SIM->SCGC4,
112 .scgc_bit = SIM_SCGC4_UART0_SHIFT,
118#define UART_0_ISR (isr_uart0_rx_tx)
120#define UART_NUMOF ARRAY_SIZE(uart_config)
162 .chan = (0 | ADC_SC1_DIFF_MASK), .avg =
ADC_AVG_MAX
174 .chan = (0 | ADC_SC1_DIFF_MASK), .avg =
ADC_AVG_MAX
186 .chan = (1 | ADC_SC1_DIFF_MASK), .avg =
ADC_AVG_MAX
198 .chan = (1 | ADC_SC1_DIFF_MASK), .avg =
ADC_AVG_MAX
218#define ADC_NUMOF ARRAY_SIZE(adc_config)
225#define ADC_REF_SETTING 0
246#define PWM_NUMOF ARRAY_SIZE(pwm_config)
261 SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) |
262 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
263 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
264 SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
267 SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) |
268 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
269 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
270 SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
273 SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) |
274 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
275 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
276 SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
279 SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) |
280 SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
281 SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
282 SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
285 SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) |
286 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
287 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
288 SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
306 .simmask = SIM_SCGC6_SPI0_MASK
310#define SPI_NUMOF ARRAY_SIZE(spi_config)
325 .scl_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
326 .sda_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
329#define I2C_NUMOF ARRAY_SIZE(i2c_config)
330#define I2C_0_ISR (isr_i2c0)
331#define I2C_1_ISR (isr_i2c1)
#define CLOCK_CORECLOCK
Clock configuration.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
#define SPI_CS_UNDEF
Define value for unused CS line.
#define UART0
UART0 register bank.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
#define ADC_AVG_NONE
Disable hardware averaging.
@ KINETIS_UART
Kinetis UART module type.
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
ADC device configuration.
I2C configuration structure.
PWM device configuration.
SPI device configuration.
UART device configuration.