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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2014 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2015 PHYTEC Messtechnik GmbH
4 * SPDX-FileCopyrightText: 2023 Hugues Larrive
5 * SPDX-License-Identifier: LGPL-2.1-only
6 */
7
8#pragma once
9
20
21#include "periph_cpu.h"
22
23#ifdef __cplusplus
24extern "C"
25{
26#endif
27
32static const clock_config_t clock_config = {
33 /*
34 * This configuration results in the system running from the PLL output with
35 * the following clock frequencies:
36 * Core: 60 MHz
37 * Bus: 60 MHz
38 * Flex: 20 MHz
39 * Flash: 20 MHz
40 */
41 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
42 SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
43 .rtc_clc = 0, /* External load caps on board */
44 .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
45 .clock_flags =
46 /* No OSC0_EN, use EXTAL directly without OSC0 */
47 KINETIS_CLOCK_RTCOSC_EN |
48 KINETIS_CLOCK_USE_FAST_IRC |
49 0,
50 .default_mode = KINETIS_MCG_MODE_PEE,
51 /* The board has an external RMII (Ethernet) clock which drives the ERC at 50 MHz */
52 .erc_range = KINETIS_MCG_ERC_RANGE_VERY_HIGH,
53 .osc_clc = 0, /* External load caps on board */
54 .oscsel = MCG_C7_OSCSEL(0), /* Use EXTAL for external clock */
55 .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
56 .fll_frdiv = MCG_C1_FRDIV(0b111), /* Divide by 1536 => FLL input 32252 Hz */
57 .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
58 .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 62.5 MHz */
59 .pll_prdiv = MCG_C5_PRDIV0(0b10011), /* Divide by 20 */
60 .pll_vdiv = MCG_C6_VDIV0(0b00000), /* Multiply by 24 => PLL freq = 60 MHz */
61};
62#define CLOCK_CORECLOCK (60000000ul)
63#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
65
70#define PIT_NUMOF (2U)
71#define PIT_CONFIG { \
72 { \
73 .prescaler_ch = 0, \
74 .count_ch = 1, \
75 }, \
76 { \
77 .prescaler_ch = 2, \
78 .count_ch = 3, \
79 }, \
80 }
81#define LPTMR_NUMOF (1U)
82#define LPTMR_CONFIG { \
83 { \
84 .dev = LPTMR0, \
85 .irqn = LPTMR0_IRQn, \
86 .src = 2, \
87 .base_freq = 32768u, \
88 }, \
89}
90#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
91
92#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
93#define PIT_ISR_0 isr_pit1
94#define PIT_ISR_1 isr_pit3
95#define LPTMR_ISR_0 isr_lptmr0
97
102static const uart_conf_t uart_config[] = {
103 {
104 .dev = UART0,
105 .freq = CLOCK_CORECLOCK,
106 .pin_rx = GPIO_PIN(PORT_B, 16),
107 .pin_tx = GPIO_PIN(PORT_B, 17),
108 .pcr_rx = PORT_PCR_MUX(3),
109 .pcr_tx = PORT_PCR_MUX(3),
110 .irqn = UART0_RX_TX_IRQn,
111 .scgc_addr = &SIM->SCGC4,
112 .scgc_bit = SIM_SCGC4_UART0_SHIFT,
113 .mode = UART_MODE_8N1,
114 .type = KINETIS_UART,
115 },
116};
117
118#define UART_0_ISR (isr_uart0_rx_tx)
119
120#define UART_NUMOF ARRAY_SIZE(uart_config)
122
127static const adc_conf_t adc_config[] = {
128 [ 0] = { /* PTB2 (Arduino A0) */
129 .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2),
130 .chan = 12, .avg = ADC_AVG_MAX
131 },
132 [ 1] = { /* PTB3 (Arduino A1) */
133 .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3),
134 .chan = 13, .avg = ADC_AVG_MAX
135 },
136 [ 2] = { /* PTB10 (Arduino A2) */
137 .dev = ADC1, .pin = GPIO_PIN(PORT_B, 10),
138 .chan = 14, .avg = ADC_AVG_MAX
139 },
140 [ 3] = { /* PTB11 (Arduino A3) */
141 .dev = ADC1, .pin = GPIO_PIN(PORT_B, 11),
142 .chan = 15, .avg = ADC_AVG_MAX
143 },
144 [ 4] = { /* PTC11 (Arduino A4) */
145 .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11),
146 .chan = 7, .avg = ADC_AVG_MAX
147 },
148 [ 5] = { /* PTC10 (Arduino A5) */
149 .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10),
150 .chan = 6, .avg = ADC_AVG_MAX
151 },
152 [ 6] = { /* ADC0_DP0 */
153 .dev = ADC0, .pin = GPIO_UNDEF,
154 .chan = 0, .avg = ADC_AVG_MAX
155 },
156 [ 7] = { /* ADC0_DM0 */
157 .dev = ADC0, .pin = GPIO_UNDEF,
158 .chan = 19, .avg = ADC_AVG_MAX
159 },
160 [ 8] = { /* ADC0_DP0 - ADC0_DM0 */
161 .dev = ADC0, .pin = GPIO_UNDEF,
162 .chan = (0 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
163 },
164 [ 9] = { /* ADC1_DP0 */
165 .dev = ADC1, .pin = GPIO_UNDEF,
166 .chan = 0, .avg = ADC_AVG_MAX
167 },
168 [10] = { /* ADC1_DM0 */
169 .dev = ADC1, .pin = GPIO_UNDEF,
170 .chan = 19, .avg = ADC_AVG_MAX
171 },
172 [11] = { /* ADC1_DP0 - ADC1_DM0 */
173 .dev = ADC1, .pin = GPIO_UNDEF,
174 .chan = (0 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
175 },
176 [12] = { /* ADC0_DP1 */
177 .dev = ADC0, .pin = GPIO_UNDEF,
178 .chan = 1, .avg = ADC_AVG_MAX
179 },
180 [13] = { /* ADC0_DM1 */
181 .dev = ADC0, .pin = GPIO_UNDEF,
182 .chan = 20, .avg = ADC_AVG_MAX
183 },
184 [14] = { /* ADC0_DP1 - ADC0_DM1 */
185 .dev = ADC0, .pin = GPIO_UNDEF,
186 .chan = (1 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
187 },
188 [15] = { /* ADC1_DP1 */
189 .dev = ADC1, .pin = GPIO_UNDEF,
190 .chan = 1, .avg = ADC_AVG_MAX
191 },
192 [16] = { /* ADC1_DM1 */
193 .dev = ADC1, .pin = GPIO_UNDEF,
194 .chan = 20, .avg = ADC_AVG_MAX
195 },
196 [17] = { /* ADC1_DP1 - ADC1_DM1 */
197 .dev = ADC1, .pin = GPIO_UNDEF,
198 .chan = (1 | ADC_SC1_DIFF_MASK), .avg = ADC_AVG_MAX
199 },
200 /* internal: temperature sensor */
201 /* The temperature sensor has a very high output impedance, it must
202 * not be sampled using hardware averaging, or the sampled values
203 * will be garbage */
204 [18] = {
205 .dev = ADC0, .pin = GPIO_UNDEF,
206 .chan = 26, .avg = ADC_AVG_NONE
207 },
208 /* internal: band gap */
209 /* Note: the band gap buffer uses a bit of current and is turned off
210 * by default, set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading
211 * or the input will be floating */
212 [19] = {
213 .dev = ADC0, .pin = GPIO_UNDEF,
214 .chan = 27, .avg = ADC_AVG_MAX
215 },
216};
217
218#define ADC_NUMOF ARRAY_SIZE(adc_config)
219/*
220 * K64F ADC reference settings:
221 * 0: VREFH/VREFL external pin pair
222 * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
223 * 2-3: reserved
224 */
225#define ADC_REF_SETTING 0
227
232static const pwm_conf_t pwm_config[] = {
233 {
234 .ftm = FTM0,
235 .chan = {
236 { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
237 { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
238 { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
239 { .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
240 },
241 .chan_numof = 4,
242 .ftm_num = 0
243 }
244};
245
246#define PWM_NUMOF ARRAY_SIZE(pwm_config)
248
259static const uint32_t spi_clk_config[] = {
260 (
261 SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
262 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
263 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
264 SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
265 ),
266 (
267 SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
268 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
269 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
270 SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
271 ),
272 (
273 SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
274 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
275 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
276 SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
277 ),
278 (
279 SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
280 SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
281 SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
282 SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
283 ),
284 (
285 SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
286 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
287 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
288 SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
289 )
290};
291
292static const spi_conf_t spi_config[] = {
293 {
294 .dev = SPI0,
295 .pin_miso = GPIO_PIN(PORT_D, 3),
296 .pin_mosi = GPIO_PIN(PORT_D, 2),
297 .pin_clk = GPIO_PIN(PORT_D, 1),
298 .pin_cs = {
299 GPIO_PIN(PORT_D, 0),
304 },
305 .pcr = GPIO_AF_2,
306 .simmask = SIM_SCGC6_SPI0_MASK
307 }
308};
309
310#define SPI_NUMOF ARRAY_SIZE(spi_config)
312
317static const i2c_conf_t i2c_config[] = {
318 {
319 .i2c = I2C0,
320 .scl_pin = GPIO_PIN(PORT_E, 24),
321 .sda_pin = GPIO_PIN(PORT_E, 25),
322 .freq = CLOCK_BUSCLOCK,
323 .speed = I2C_SPEED_FAST,
324 .irqn = I2C0_IRQn,
325 .scl_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
326 .sda_pcr = (PORT_PCR_MUX(5) | PORT_PCR_ODE_MASK),
327 },
328};
329#define I2C_NUMOF ARRAY_SIZE(i2c_config)
330#define I2C_0_ISR (isr_i2c0)
331#define I2C_1_ISR (isr_i2c1)
333
334#ifdef __cplusplus
335}
336#endif
337
#define CLOCK_CORECLOCK
Clock configuration.
Definition periph_cpu.h:28
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_E
port E
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:43
@ PORT_D
port D
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:275
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
Definition periph_cpu.h:278
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
#define UART0
UART0 register bank.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition mcg.h:146
#define ADC_AVG_NONE
Disable hardware averaging.
Definition periph_cpu.h:369
@ KINETIS_UART
Kinetis UART module type.
Definition periph_cpu.h:537
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition periph_cpu.h:293
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
Definition periph_cpu.h:373
ADC device configuration.
Definition periph_cpu.h:374
I2C configuration structure.
Definition periph_cpu.h:295
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214