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periph_conf.h
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1/*
2 * Copyright (C) 2018 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* Add specific clock configuration (HSE, LSE) for this board here */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27#include "periph_cpu.h"
28#include "clk_conf.h"
29#include "cfg_i2c1_pb8_pb9.h"
30#include "cfg_rtt_default.h"
31#include "cfg_usb_otg_fs.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
41static const timer_conf_t timer_config[] = {
42 {
43 .dev = TIM5,
44 .max = 0xffffffff,
45 .rcc_mask = RCC_APB1ENR1_TIM5EN,
46 .bus = APB1,
47 .irqn = TIM5_IRQn
48 }
49};
50
51#define TIMER_0_ISR isr_tim5
52
53#define TIMER_NUMOF ARRAY_SIZE(timer_config)
60static const uart_conf_t uart_config[] = {
61 {
62 .dev = LPUART1,
63 .rcc_mask = RCC_APB1ENR2_LPUART1EN,
64 .rx_pin = GPIO_PIN(PORT_G, 8),
65 .tx_pin = GPIO_PIN(PORT_G, 7),
66 .rx_af = GPIO_AF8,
67 .tx_af = GPIO_AF8,
68 .bus = APB12,
69 .irqn = LPUART1_IRQn,
70 .type = STM32_LPUART,
71 .clk_src = 0,
72 },
73 {
74 .dev = USART3,
75 .rcc_mask = RCC_APB1ENR1_USART3EN,
76 .rx_pin = GPIO_PIN(PORT_D, 9),
77 .tx_pin = GPIO_PIN(PORT_D, 8),
78 .rx_af = GPIO_AF7,
79 .tx_af = GPIO_AF7,
80 .bus = APB1,
81 .irqn = USART3_IRQn,
82 .type = STM32_USART,
83 .clk_src = 0, /* Use APB clock */
84#ifdef UART_USE_DMA
85 .dma_stream = 6,
86 .dma_chan = 4
87#endif
88 }
89};
90
91#define UART_0_ISR (isr_lpuart1)
92#define UART_1_ISR (isr_usart3)
93
94#define UART_NUMOF ARRAY_SIZE(uart_config)
101static const spi_conf_t spi_config[] = {
102 {
103 .dev = SPI1,
104 .mosi_pin = GPIO_PIN(PORT_A, 7),
105 .miso_pin = GPIO_PIN(PORT_A, 6),
106 .sclk_pin = GPIO_PIN(PORT_A, 5),
107 .cs_pin = SPI_CS_UNDEF,
108 .mosi_af = GPIO_AF5,
109 .miso_af = GPIO_AF5,
110 .sclk_af = GPIO_AF5,
111 .cs_af = GPIO_AF5,
112 .rccmask = RCC_APB2ENR_SPI1EN,
113 .apbbus = APB2
114 }
115};
116
117#define SPI_NUMOF ARRAY_SIZE(spi_config)
148static const adc_conf_t adc_config[] = {
149 { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 8 }, /* ADC12_IN8 */
150 { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 1 }, /* ADC123_IN1 */
151 { .pin = GPIO_PIN(PORT_C, 3), .dev = 0, .chan = 4 }, /* ADC123_IN4 */
152 { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* ADC123_IN2 */
153 { .pin = GPIO_PIN(PORT_C, 4), .dev = 0, .chan = 13 }, /* ADC12_IN13 */
154 { .pin = GPIO_PIN(PORT_C, 5), .dev = 0, .chan = 14 }, /* ADC12_IN14 */
155 { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, /* VBAT */
156};
157
161#define ADC_NUMOF ARRAY_SIZE(adc_config)
162
166#define VBAT_ADC ADC_LINE(6)
167
187static const pwm_conf_t pwm_config[] = {
188 {
189 .dev = TIM2,
190 .rcc_mask = RCC_APB1ENR1_TIM2EN,
191 .chan = { { .pin = GPIO_PIN(PORT_A, 0) /* CN10 D32 */, .cc_chan = 0},
192 { .pin = GPIO_PIN(PORT_A, 1) /* CN10 A8 */, .cc_chan = 1},
193 { .pin = GPIO_PIN(PORT_A, 2) /* CN10 D26 */, .cc_chan = 2},
194 { .pin = GPIO_PIN(PORT_A, 3) /* CN9 A0 */, .cc_chan = 3} },
195 .af = GPIO_AF1,
196 .bus = APB1
197 },
198 {
199 .dev = TIM3,
200 .rcc_mask = RCC_APB1ENR1_TIM3EN,
201 .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* CN7 D25 */, .cc_chan = 0},
202 { .pin = GPIO_PIN(PORT_E, 4) /* CN9 D57 */, .cc_chan = 1},
203 { .pin = GPIO_PIN(PORT_B, 0) /* CN10 D33 */, .cc_chan = 2},
204 { .pin = GPIO_PIN(PORT_B, 1) /* CN10 A6 */, .cc_chan = 3} },
205 .af = GPIO_AF2,
206 .bus = APB1
207 },
208};
209
210#define PWM_NUMOF ARRAY_SIZE(pwm_config)
211
214#ifdef __cplusplus
215}
216#endif
217
218#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_G
port G
Definition periph_cpu.h:53
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const adc_conf_t adc_config[]
ADC configuration.
Common configuration for STM32 I2C.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:111
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:39
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
gpio_t pin
pin connected to the channel
Definition periph_cpu.h:288
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219