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periph_conf.h
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1/*
2 * Copyright (C) 2017 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* This board provides an LSE */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27/* This board provides an HSE */
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
30#endif
31
32#include "periph_cpu.h"
33#include "clk_conf.h"
34#include "cfg_i2c1_pb8_pb9.h"
35#include "cfg_rtt_default.h"
36#include "cfg_timer_tim2.h"
37#include "cfg_usb_otg_fs.h"
38#include "mii.h"
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
48static const dma_conf_t dma_config[] = {
49 { .stream = 4 }, /* DMA1 Stream 4 - USART3_TX */
50 { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
51 { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
52 { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
53};
54
55#define DMA_0_ISR isr_dma1_stream4
56#define DMA_1_ISR isr_dma2_stream6
57#define DMA_2_ISR isr_dma1_stream6
58#define DMA_3_ISR isr_dma2_stream0
59
60#define DMA_NUMOF ARRAY_SIZE(dma_config)
67static const uart_conf_t uart_config[] = {
68 {
69 .dev = USART3,
70 .rcc_mask = RCC_APB1ENR_USART3EN,
71 .rx_pin = GPIO_PIN(PORT_D, 9),
72 .tx_pin = GPIO_PIN(PORT_D, 8),
73 .rx_af = GPIO_AF7,
74 .tx_af = GPIO_AF7,
75 .bus = APB1,
76 .irqn = USART3_IRQn,
77#ifdef MODULE_PERIPH_DMA
78 .dma = 0,
79 .dma_chan = 7
80#endif
81 },
82 {
83 .dev = USART6,
84 .rcc_mask = RCC_APB2ENR_USART6EN,
85 .rx_pin = GPIO_PIN(PORT_G, 9),
86 .tx_pin = GPIO_PIN(PORT_G, 14),
87 .rx_af = GPIO_AF8,
88 .tx_af = GPIO_AF8,
89 .bus = APB2,
90 .irqn = USART6_IRQn,
91#ifdef MODULE_PERIPH_DMA
92 .dma = 1,
93 .dma_chan = 5
94#endif
95 },
96 {
97 .dev = USART2,
98 .rcc_mask = RCC_APB1ENR_USART2EN,
99 .rx_pin = GPIO_PIN(PORT_D, 6),
100 .tx_pin = GPIO_PIN(PORT_D, 5),
101 .rx_af = GPIO_AF7,
102 .tx_af = GPIO_AF7,
103 .bus = APB1,
104 .irqn = USART2_IRQn,
105#ifdef MODULE_PERIPH_DMA
106 .dma = 2,
107 .dma_chan = 4
108#endif
109 }
110};
111
112#define UART_0_ISR (isr_usart3)
113#define UART_1_ISR (isr_usart6)
114#define UART_2_ISR (isr_usart2)
115
116#define UART_NUMOF ARRAY_SIZE(uart_config)
123static const spi_conf_t spi_config[] = {
124 {
125 .dev = SPI1,
126 /* PA7 is the default MOSI pin, as it is required for compatibility with
127 * Arduino(ish) shields. Sadly, it is also connected to the RMII_DV of
128 * Ethernet PHY. We work around this by remapping the MOSI to PB5 when
129 * the on-board Ethernet PHY is used.
130 */
131#ifdef MODULE_PERIPH_ETH
132 .mosi_pin = GPIO_PIN(PORT_B, 5),
133#else
134 .mosi_pin = GPIO_PIN(PORT_A, 7),
135#endif
136 .miso_pin = GPIO_PIN(PORT_A, 6),
137 .sclk_pin = GPIO_PIN(PORT_A, 5),
138 .cs_pin = SPI_CS_UNDEF,
139 .mosi_af = GPIO_AF5,
140 .miso_af = GPIO_AF5,
141 .sclk_af = GPIO_AF5,
142 .cs_af = GPIO_AF5,
143 .rccmask = RCC_APB2ENR_SPI1EN,
144 .apbbus = APB2
145 },
146 {
147 .dev = SPI4,
148 .mosi_pin = GPIO_PIN(PORT_E, 6),
149 .miso_pin = GPIO_PIN(PORT_E, 5),
150 .sclk_pin = GPIO_PIN(PORT_E, 2),
151 .cs_pin = SPI_CS_UNDEF,
152 .mosi_af = GPIO_AF5,
153 .miso_af = GPIO_AF5,
154 .sclk_af = GPIO_AF5,
155 .cs_af = GPIO_AF5,
156 .rccmask = RCC_APB2ENR_SPI4EN,
157 .apbbus = APB2
158 }
159};
160
161#define SPI_NUMOF ARRAY_SIZE(spi_config)
168static const eth_conf_t eth_config = {
169 .mode = RMII,
171 .dma = 3,
172 .dma_chan = 8,
173 .phy_addr = 0x00,
174 .pins = {
175 GPIO_PIN(PORT_G, 13),
176 GPIO_PIN(PORT_B, 13),
177 GPIO_PIN(PORT_G, 11),
178 GPIO_PIN(PORT_C, 4),
179 GPIO_PIN(PORT_C, 5),
180 GPIO_PIN(PORT_A, 7),
181 GPIO_PIN(PORT_C, 1),
182 GPIO_PIN(PORT_A, 2),
183 GPIO_PIN(PORT_A, 1),
184 }
185};
186
187#define ETH_DMA_ISR isr_dma2_stream0
200static const adc_conf_t adc_config[] = {
201 {GPIO_PIN(PORT_A, 3), 2, 3},
202 {GPIO_PIN(PORT_C, 0), 2, 10},
203 {GPIO_PIN(PORT_C, 3), 2, 13},
204 {GPIO_PIN(PORT_F, 3), 2, 9},
205 {GPIO_PIN(PORT_F, 5), 2, 15},
206 {GPIO_PIN(PORT_F, 10), 2, 8},
207 {GPIO_UNDEF, 0, 18}, /* VBAT */
208};
209
210#define VBAT_ADC ADC_LINE(6)
211#define ADC_NUMOF ARRAY_SIZE(adc_config)
221static const pwm_conf_t pwm_config[] = {
222 {
223 .dev = TIM1,
224 .rcc_mask = RCC_APB2ENR_TIM1EN,
225 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 CN10-4 */, .cc_chan = 0},
226 { .pin = GPIO_PIN(PORT_E, 11) /* D5 CN10-6 */, .cc_chan = 1},
227 { .pin = GPIO_PIN(PORT_E, 13) /* D3 CN10-10 */, .cc_chan = 2},
228 { .pin = GPIO_PIN(PORT_E, 14) /* D38 CN10-28 */, .cc_chan = 3} },
229 .af = GPIO_AF1,
230 .bus = APB2
231 },
232 {
233 .dev = TIM4,
234 .rcc_mask = RCC_APB1ENR_TIM4EN,
235 .chan = { { .pin = GPIO_PIN(PORT_D, 12) /* D29 CN10-21 */, .cc_chan = 0},
236 { .pin = GPIO_PIN(PORT_D, 13) /* D28 CN10-19 */, .cc_chan = 1},
237 { .pin = GPIO_PIN(PORT_D, 14) /* D10 CN7-16 */, .cc_chan = 2},
238 { .pin = GPIO_PIN(PORT_D, 15) /* D9 CN7-18 */, .cc_chan = 3} },
239 .af = GPIO_AF2,
240 .bus = APB1
241 },
242};
243
247#define PWM_NUMOF ARRAY_SIZE(pwm_config)
250#ifdef __cplusplus
251}
252#endif
253
254#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_G
port G
Definition periph_cpu.h:53
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_F
port F
Definition periph_cpu.h:52
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition cpu_eth.h:37
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:111
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition mii.h:69
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition mii.h:73
Interface definition for MII/RMII h.
ADC device configuration.
Definition periph_cpu.h:379
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
Ethernet Peripheral configuration.
Definition cpu_eth.h:44
eth_mode_t mode
Select configuration mode.
Definition cpu_eth.h:45
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219