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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2015 Lari Lehtomäki
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_i2c1_pb8_pb9.h"
31#include "cfg_timer_tim5.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
41static const dma_conf_t dma_config[] = {
42 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
43 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
44 { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
45 { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
46 { .stream = 5 }, /* DMA1 Stream 5 - SPI3_TX */
47 { .stream = 0 }, /* DMA1 Stream 0 - SPI3_RX */
48};
49
50#define DMA_0_ISR isr_dma2_stream3
51#define DMA_1_ISR isr_dma2_stream2
52#define DMA_2_ISR isr_dma1_stream4
53#define DMA_3_ISR isr_dma1_stream3
54#define DMA_4_ISR isr_dma1_stream5
55#define DMA_5_ISR isr_dma1_stream0
56
57#define DMA_NUMOF ARRAY_SIZE(dma_config)
59
64static const uart_conf_t uart_config[] = {
65 {
66 .dev = USART2,
67 .rcc_mask = RCC_APB1ENR_USART2EN,
68 .rx_pin = GPIO_PIN(PORT_A, 3),
69 .tx_pin = GPIO_PIN(PORT_A, 2),
70 .rx_af = GPIO_AF7,
71 .tx_af = GPIO_AF7,
72 .bus = APB1,
73 .irqn = USART2_IRQn,
74#ifdef MODULE_PERIPH_DMA
75 .dma = DMA_STREAM_UNDEF,
76 .dma_chan = UINT8_MAX,
77#endif
78 },
79 {
80 .dev = USART1,
81 .rcc_mask = RCC_APB2ENR_USART1EN,
82 .rx_pin = GPIO_PIN(PORT_A, 10),
83 .tx_pin = GPIO_PIN(PORT_A, 9),
84 .rx_af = GPIO_AF7,
85 .tx_af = GPIO_AF7,
86 .bus = APB2,
87 .irqn = USART1_IRQn,
88#ifdef MODULE_PERIPH_DMA
89 .dma = DMA_STREAM_UNDEF,
90 .dma_chan = UINT8_MAX,
91#endif
92 },
93 {
94 .dev = USART6,
95 .rcc_mask = RCC_APB2ENR_USART6EN,
96 .rx_pin = GPIO_PIN(PORT_A, 12),
97 .tx_pin = GPIO_PIN(PORT_A, 11),
98 .rx_af = GPIO_AF8,
99 .tx_af = GPIO_AF8,
100 .bus = APB2,
101 .irqn = USART6_IRQn,
102#ifdef MODULE_PERIPH_DMA
103 .dma = DMA_STREAM_UNDEF,
104 .dma_chan = UINT8_MAX,
105#endif
106 }
107};
108
109#define UART_0_ISR (isr_usart2)
110#define UART_1_ISR (isr_usart1)
111#define UART_2_ISR (isr_usart6)
112
113#define UART_NUMOF ARRAY_SIZE(uart_config)
115
120static const pwm_conf_t pwm_config[] = {
121 {
122 .dev = TIM2,
123 .rcc_mask = RCC_APB1ENR_TIM2EN,
124 .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
125 { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
126 { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
127 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
128 .af = GPIO_AF1,
129 .bus = APB1
130 },
131};
132
133#define PWM_NUMOF ARRAY_SIZE(pwm_config)
135
140static const qdec_conf_t qdec_config[] = {
141 {
142 .dev = TIM3,
143 .max = 0xffffffff,
144 .rcc_mask = RCC_APB1ENR_TIM3EN,
145 .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
146 { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 } },
147 .af = GPIO_AF2,
148 .bus = APB1,
149 .irqn = TIM3_IRQn
150 },
151 {
152 .dev = TIM4,
153 .max = 0xffffffff,
154 .rcc_mask = RCC_APB1ENR_TIM4EN,
155 .chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
156 { .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
157 .af = GPIO_AF2,
158 .bus = APB1,
159 .irqn = TIM4_IRQn
160 },
161};
162
163#define QDEC_0_ISR isr_tim3
164#define QDEC_1_ISR isr_tim4
165
166#define QDEC_NUMOF ARRAY_SIZE(qdec_config)
168
173static const spi_conf_t spi_config[] = {
174 {
175 .dev = SPI1,
176 .mosi_pin = GPIO_PIN(PORT_A, 7),
177 .miso_pin = GPIO_PIN(PORT_A, 6),
178 .sclk_pin = GPIO_PIN(PORT_A, 5),
179 .cs_pin = GPIO_PIN(PORT_A, 4),
180 .mosi_af = GPIO_AF5,
181 .miso_af = GPIO_AF5,
182 .sclk_af = GPIO_AF5,
183 .cs_af = GPIO_AF5,
184 .rccmask = RCC_APB2ENR_SPI1EN,
185 .apbbus = APB2,
186#ifdef MODULE_PERIPH_DMA
187 .tx_dma = 0,
188 .tx_dma_chan = 3,
189 .rx_dma = 1,
190 .rx_dma_chan = 3,
191#endif
192 },
193 {
194 .dev = SPI2,
195 .mosi_pin = GPIO_PIN(PORT_B, 15),
196 .miso_pin = GPIO_PIN(PORT_B, 14),
197 .sclk_pin = GPIO_PIN(PORT_B, 13),
198 .cs_pin = GPIO_PIN(PORT_B, 12),
199 .mosi_af = GPIO_AF5,
200 .miso_af = GPIO_AF5,
201 .sclk_af = GPIO_AF5,
202 .cs_af = GPIO_AF5,
203 .rccmask = RCC_APB1ENR_SPI2EN,
204 .apbbus = APB1,
205#ifdef MODULE_PERIPH_DMA
206 .tx_dma = 2,
207 .tx_dma_chan = 0,
208 .rx_dma = 3,
209 .rx_dma_chan = 0,
210#endif
211 },
212 {
213 .dev = SPI3,
214 .mosi_pin = GPIO_PIN(PORT_C, 12),
215 .miso_pin = GPIO_PIN(PORT_C, 11),
216 .sclk_pin = GPIO_PIN(PORT_C, 10),
217 .cs_pin = GPIO_UNDEF,
218 .mosi_af = GPIO_AF6,
219 .miso_af = GPIO_AF6,
220 .sclk_af = GPIO_AF6,
221 .cs_af = GPIO_AF6,
222 .rccmask = RCC_APB1ENR_SPI3EN,
223 .apbbus = APB1,
224#ifdef MODULE_PERIPH_DMA
225 .tx_dma = 4,
226 .tx_dma_chan = 0,
227 .rx_dma = 5,
228 .rx_dma_chan = 0,
229#endif
230 }
231};
232
233#define SPI_NUMOF ARRAY_SIZE(spi_config)
235
246static const adc_conf_t adc_config[] = {
247 {GPIO_PIN(PORT_A, 0), 0, 0},
248 {GPIO_PIN(PORT_A, 1), 0, 1},
249 {GPIO_PIN(PORT_A, 4), 0, 4},
250 {GPIO_PIN(PORT_B, 0), 0, 8},
251 {GPIO_PIN(PORT_C, 1), 0, 11},
252 {GPIO_PIN(PORT_C, 0), 0, 10},
253 {GPIO_UNDEF, 0, 18}, /* VBAT */
254};
255
256#define VBAT_ADC ADC_LINE(6)
257#define ADC_NUMOF ARRAY_SIZE(adc_config)
259
260#ifdef __cplusplus
261}
262#endif
263
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF6
use alternate function 6
Definition cpu_gpio.h:107
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
DMA configuration.
Definition cpu_dma.h:31
PWM device configuration.
Quadrature decoder configuration struct.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217