19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
28#include "periph_cpu.h"
50#define DMA_0_ISR isr_dma2_stream3
51#define DMA_1_ISR isr_dma2_stream2
52#define DMA_2_ISR isr_dma1_stream4
53#define DMA_3_ISR isr_dma1_stream3
54#define DMA_4_ISR isr_dma1_stream5
55#define DMA_5_ISR isr_dma1_stream0
57#define DMA_NUMOF ARRAY_SIZE(dma_config)
67 .rcc_mask = RCC_APB1ENR_USART2EN,
74#ifdef MODULE_PERIPH_DMA
75 .dma = DMA_STREAM_UNDEF,
76 .dma_chan = UINT8_MAX,
81 .rcc_mask = RCC_APB2ENR_USART1EN,
88#ifdef MODULE_PERIPH_DMA
89 .dma = DMA_STREAM_UNDEF,
90 .dma_chan = UINT8_MAX,
95 .rcc_mask = RCC_APB2ENR_USART6EN,
102#ifdef MODULE_PERIPH_DMA
103 .dma = DMA_STREAM_UNDEF,
104 .dma_chan = UINT8_MAX,
109#define UART_0_ISR (isr_usart2)
110#define UART_1_ISR (isr_usart1)
111#define UART_2_ISR (isr_usart6)
113#define UART_NUMOF ARRAY_SIZE(uart_config)
123 .rcc_mask = RCC_APB1ENR_TIM2EN,
133#define PWM_NUMOF ARRAY_SIZE(pwm_config)
144 .rcc_mask = RCC_APB1ENR_TIM3EN,
154 .rcc_mask = RCC_APB1ENR_TIM4EN,
163#define QDEC_0_ISR isr_tim3
164#define QDEC_1_ISR isr_tim4
166#define QDEC_NUMOF ARRAY_SIZE(qdec_config)
184 .rccmask = RCC_APB2ENR_SPI1EN,
186#ifdef MODULE_PERIPH_DMA
203 .rccmask = RCC_APB1ENR_SPI2EN,
205#ifdef MODULE_PERIPH_DMA
222 .rccmask = RCC_APB1ENR_SPI3EN,
224#ifdef MODULE_PERIPH_DMA
233#define SPI_NUMOF ARRAY_SIZE(spi_config)
256#define VBAT_ADC ADC_LINE(6)
257#define ADC_NUMOF ARRAY_SIZE(adc_config)
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
@ GPIO_AF1
use alternate function 1
@ GPIO_AF2
use alternate function 2
@ GPIO_AF5
use alternate function 5
@ GPIO_AF8
use alternate function 8
@ GPIO_AF6
use alternate function 6
@ GPIO_AF7
use alternate function 7
@ APB1
Advanced Peripheral Bus 1.
@ APB2
Advanced Peripheral Bus 2.
ADC device configuration.
PWM device configuration.
Quadrature decoder configuration struct.
SPI device configuration.
UART device configuration.