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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2025 TU Dresden
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20# define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25# define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28/* The HSE provides a 8MHz clock */
29#ifndef CONFIG_CLOCK_HSE
30# define CONFIG_CLOCK_HSE MHZ(8)
31#endif
32
33#include "periph_cpu.h"
34#include "clk_conf.h"
35#include "cfg_usb_otg_fs.h"
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
45static const dma_conf_t dma_config[] = {
46 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
47 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
48 { .stream = 3 }, /* DMA1 Stream 3 - USART3_TX */
49 { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
50};
51
52#define DMA_0_ISR isr_dma2_stream3
53#define DMA_1_ISR isr_dma2_stream2
54#define DMA_2_ISR isr_dma1_stream3
55#define DMA_3_ISR isr_dma1_stream6
56
57#define DMA_NUMOF ARRAY_SIZE(dma_config)
59
67static const timer_conf_t timer_config[] = {
68 {
69 .dev = TIM5,
70 .max = 0xffffffff,
71 .rcc_mask = RCC_APB1ENR_TIM5EN,
72 .bus = APB1,
73 .irqn = TIM5_IRQn,
74 }
75};
76
77#define TIMER_0_ISR isr_tim5
78
79#define TIMER_NUMOF ARRAY_SIZE(timer_config)
81
86static const uart_conf_t uart_config[] = {
87 {
88 .dev = USART3,
89 .rcc_mask = RCC_APB1ENR_USART3EN,
90 .rx_pin = GPIO_PIN(PORT_C, 11),
91 .tx_pin = GPIO_PIN(PORT_C, 10),
92 .rx_af = GPIO_AF7,
93 .tx_af = GPIO_AF7,
94 .bus = APB1,
95 .irqn = USART3_IRQn,
96#ifdef MODULE_PERIPH_DMA
97 .dma = 2,
98 .dma_chan = 4
99#endif
100 },
101 {
102 .dev = USART2,
103 .rcc_mask = RCC_APB1ENR_USART2EN,
104 .rx_pin = GPIO_PIN(PORT_A, 3),
105 .tx_pin = GPIO_PIN(PORT_A, 2),
106 .rx_af = GPIO_AF7,
107 .tx_af = GPIO_AF7,
108 .bus = APB1,
109 .irqn = USART2_IRQn,
110#ifdef MODULE_PERIPH_DMA
111 .dma = 3,
112 .dma_chan = 4
113#endif
114 }
115};
116
117#define UART_0_ISR (isr_usart3)
118#define UART_1_ISR (isr_usart2)
119
120#define UART_NUMOF ARRAY_SIZE(uart_config)
122
127static const adc_conf_t adc_config[] = {
128 { .pin = GPIO_PIN(PORT_A, 2), .dev = 0, .chan = 2 },
129 { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 3 },
130 { .pin = GPIO_PIN(PORT_A, 5), .dev = 1, .chan = 5 },
131 { .pin = GPIO_PIN(PORT_A, 6), .dev = 1, .chan = 6 },
132 { .pin = GPIO_PIN(PORT_A, 7), .dev = 1, .chan = 7 },
133 { .pin = GPIO_UNDEF, .dev = 0, .chan = 0}, /* VBAT */
134};
135
136/* The radio MCU takes care of power management -> adc line without proper pin. */
137#define VBAT_ADC ADC_LINE(5)
138#define ADC_NUMOF ARRAY_SIZE(adc_config)
140
145static const pwm_conf_t pwm_config[] = {
146 {
147 .dev = TIM9,
148 .rcc_mask = RCC_APB2ENR_TIM9EN,
149 .chan = {
150 { .pin = GPIO_PIN(PORT_A, 2), .cc_chan = 0 },
151 { .pin = GPIO_PIN(PORT_A, 3), .cc_chan = 1 },
152 { .pin = GPIO_UNDEF, .cc_chan = 0 },
153 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
154 .af = GPIO_AF3,
155 .bus = APB2,
156 },
157 {
158 .dev = TIM2,
159 .rcc_mask = RCC_APB1ENR_TIM2EN,
160 .chan = {
161 { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0 }, /* Motor 3 */
162 { .pin = GPIO_PIN(PORT_A, 1), .cc_chan = 1 }, /* Motor 1 */
163 { .pin = GPIO_PIN(PORT_A, 2), .cc_chan = 2 }, /* broken out */
164 { .pin = GPIO_PIN(PORT_B, 11), .cc_chan = 3 } /* Motor 2 */ },
165 .af = GPIO_AF1,
166 .bus = APB1
167 },
168 {
169 .dev = TIM4,
170 .rcc_mask = RCC_APB1ENR_TIM4EN,
171 .chan = {
172 { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 3 }, /* Motor 4 */
173 { .pin = GPIO_UNDEF, .cc_chan = 0 },
174 { .pin = GPIO_UNDEF, .cc_chan = 0 },
175 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
176 .af = GPIO_AF2,
177 .bus = APB1
178 }
179};
180
181#define PWM_NUMOF ARRAY_SIZE(pwm_config)
183
188static const spi_conf_t spi_config[] = {
189 {
190 .dev = SPI1,
191 .mosi_pin = GPIO_PIN(PORT_A, 7),
192 .miso_pin = GPIO_PIN(PORT_A, 6),
193 .sclk_pin = GPIO_PIN(PORT_A, 5),
194 .cs_pin = GPIO_UNDEF,
195 .mosi_af = GPIO_AF5,
196 .miso_af = GPIO_AF5,
197 .sclk_af = GPIO_AF5,
198 .cs_af = GPIO_AF5,
199 .rccmask = RCC_APB2ENR_SPI1EN,
200 .apbbus = APB2,
201#ifdef MODULE_PERIPH_DMA
202 .tx_dma = 0,
203 .tx_dma_chan = 3,
204 .rx_dma = 1,
205 .rx_dma_chan = 3,
206#endif
207 }
208};
209
210#define SPI_NUMOF ARRAY_SIZE(spi_config)
212
217static const i2c_conf_t i2c_config[] = {
218 {
219 .dev = I2C1,
220 .speed = I2C_SPEED_NORMAL,
221 .scl_pin = GPIO_PIN(PORT_B, 6),
222 .sda_pin = GPIO_PIN(PORT_B, 7),
223 .scl_af = GPIO_AF4,
224 .sda_af = GPIO_AF4,
225 .bus = APB1,
226 .rcc_mask = RCC_APB1ENR_I2C1EN,
227 .clk = CLOCK_APB1,
228 .irqn = I2C1_EV_IRQn
229 }
230};
231
232#define I2C_0_ISR isr_i2c1_ev
233
234#define I2C_NUMOF ARRAY_SIZE(i2c_config)
236
237#ifdef __cplusplus
238}
239#endif
240
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_A
port A
Definition periph_cpu.h:43
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:99
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:100
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:103
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:102
@ GPIO_AF3
use alternate function 3
Definition cpu_gpio.h:101
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:105
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:75
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:76
ADC device configuration.
Definition periph_cpu.h:374
DMA configuration.
Definition cpu_dma.h:28
I2C configuration structure.
Definition periph_cpu.h:295
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
Timer device configuration.
Definition periph_cpu.h:260
UART device configuration.
Definition periph_cpu.h:214