#include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_hs_phy_fs.h"
Go to the source code of this file.
◆ CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1 |
◆ CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1 |
◆ DMA_0_ISR
#define DMA_0_ISR isr_dma2_stream6 |
◆ DMA_1_ISR
#define DMA_1_ISR isr_dma2_stream5 |
◆ DMA_NUMOF
◆ FMC_BANK_NUMOF
◆ I2C_0_ISR
#define I2C_0_ISR isr_i2c3_ev |
◆ I2C_NUMOF
◆ SPI_NUMOF
◆ UART_0_ISR
#define UART_0_ISR (isr_usart1) |
◆ UART_NUMOF
◆ dma_config
Initial value:= {
{ .stream = 14 },
{ .stream = 13 },
}
Definition at line 45 of file periph_conf.h.
◆ fmc_bank_config
FMC Bank configuration.
The board has a SDRAM IS42S16400J-7TL with 64 MBit on-board. It is organized in 4 banks of 1M x 16 bits each and connected to bank 6 at address 0xd0000000.
Definition at line 200 of file periph_conf.h.
◆ fmc_config
◆ i2c_config
Initial value:= {
{
.dev = I2C3,
.rcc_mask = RCC_APB1ENR_I2C3EN,
.clk = CLOCK_APB1,
.irqn = I2C3_EV_IRQn,
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
@ GPIO_AF4
use alternate function 4
@ APB1
Advanced Peripheral Bus 1
Definition at line 115 of file periph_conf.h.
◆ spi_config
Initial value:= {
{
.dev = SPI5,
.rccmask = RCC_APB2ENR_SPI5EN,
}
}
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ GPIO_AF5
use alternate function 5
@ APB2
Advanced Peripheral Bus 2
Definition at line 86 of file periph_conf.h.
◆ uart_config
Initial value:= {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.irqn = USART1_IRQn,
}
}
@ GPIO_AF7
use alternate function 7
Definition at line 60 of file periph_conf.h.