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periph_conf.h File Reference

Peripheral MCU configuration for the nucleo-g431rb board. More...

Detailed Description

Peripheral MCU configuration for the nucleo-g431rb board.

Author
Alexandre Abadie alexa.nosp@m.ndre.nosp@m..abad.nosp@m.ie@i.nosp@m.nria..nosp@m.fr

Definition in file periph_conf.h.

#include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
+ Include dependency graph for periph_conf.h:

Go to the source code of this file.

#define CONFIG_BOARD_HAS_LSE   1
 
#define CONFIG_BOARD_HAS_HSE   1
 
#define CONFIG_CLOCK_PLL_M   (6)
 

UART configuration

#define UART_0_ISR   (isr_lpuart1)
 
#define UART_1_ISR   (isr_usart1)
 
#define UART_NUMOF   ARRAY_SIZE(uart_config)
 
static const uart_conf_t uart_config []
 

SPI configuration

#define SPI_NUMOF   ARRAY_SIZE(spi_config)
 
static const spi_conf_t spi_config []
 

PWM configuration

#define PWM_NUMOF   ARRAY_SIZE(pwm_config)
 
static const pwm_conf_t pwm_config []
 

Macro Definition Documentation

◆ CONFIG_BOARD_HAS_HSE

#define CONFIG_BOARD_HAS_HSE   1

Definition at line 28 of file periph_conf.h.

◆ CONFIG_BOARD_HAS_LSE

#define CONFIG_BOARD_HAS_LSE   1

Definition at line 24 of file periph_conf.h.

◆ CONFIG_CLOCK_PLL_M

#define CONFIG_CLOCK_PLL_M   (6)

Definition at line 32 of file periph_conf.h.

◆ PWM_NUMOF

#define PWM_NUMOF   ARRAY_SIZE(pwm_config)

Definition at line 122 of file periph_conf.h.

◆ SPI_NUMOF

#define SPI_NUMOF   ARRAY_SIZE(spi_config)

Definition at line 102 of file periph_conf.h.

◆ UART_0_ISR

#define UART_0_ISR   (isr_lpuart1)

Definition at line 76 of file periph_conf.h.

◆ UART_1_ISR

#define UART_1_ISR   (isr_usart1)

Definition at line 77 of file periph_conf.h.

◆ UART_NUMOF

#define UART_NUMOF   ARRAY_SIZE(uart_config)

Definition at line 79 of file periph_conf.h.

Variable Documentation

◆ pwm_config

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.dev = TIM3,
.rcc_mask = RCC_APB1ENR1_TIM3EN,
.chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
{ .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
.af = GPIO_AF2,
.bus = APB1
}
}
@ PORT_C
port C
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79

Definition at line 109 of file periph_conf.h.

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.mosi_af = GPIO_AF5,
.miso_af = GPIO_AF5,
.sclk_af = GPIO_AF5,
.cs_af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2,
},
}
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80

Definition at line 86 of file periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = LPUART1,
.rcc_mask = RCC_APB1ENR2_LPUART1EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF12,
.tx_af = GPIO_AF12,
.bus = APB12,
.irqn = LPUART1_IRQn,
.type = STM32_LPUART,
.clk_src = 0,
},
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_C, 5),
.tx_pin = GPIO_PIN(PORT_C, 4),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn,
.type = STM32_USART,
.clk_src = 0,
},
}
@ GPIO_AF12
use alternate function 12
Definition cpu_gpio.h:115
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:39
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38

Definition at line 49 of file periph_conf.h.