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boards/pba-d-01-kw2x/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 #define KINETIS_CPU_USE_MCG 1
37 
38 #define KINETIS_MCG_USE_ERC 1
39 #define KINETIS_MCG_USE_PLL 1
40 #define KINETIS_MCG_DCO_RANGE (24000000U)
41 #define KINETIS_MCG_ERC_OSCILLATOR 0
42 #define KINETIS_MCG_ERC_FRDIV 2
43 #define KINETIS_MCG_ERC_RANGE 1
44 #define KINETIS_MCG_ERC_FREQ 4000000
45 #define KINETIS_MCG_PLL_PRDIV 1
46 #define KINETIS_MCG_PLL_VDIV0 0
47 #define KINETIS_MCG_PLL_FREQ 48000000
48 
49 #define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
50 #define CLOCK_BUSCLOCK CLOCK_CORECLOCK
51 
57 #define PIT_NUMOF (2U)
58 #define PIT_CONFIG { \
59  { \
60  .prescaler_ch = 0, \
61  .count_ch = 1, \
62  }, \
63  { \
64  .prescaler_ch = 2, \
65  .count_ch = 3, \
66  }, \
67  }
68 #define LPTMR_NUMOF (0U)
69 #define LPTMR_CONFIG {}
70 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
71 
72 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
73 #define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
74 #define PIT_ISR_0 isr_pit1
75 #define PIT_ISR_1 isr_pit3
76 #define LPTMR_ISR_0 isr_lptmr0
77 
84 #define UART_NUMOF (1U)
85 #define UART_0_EN 1
86 #define UART_1_EN 0
87 #define UART_IRQ_PRIO 1
88 #define UART_CLK (48e6)
89 
90 /* UART 0 device configuration */
91 #define KINETIS_UART UART_Type
92 #define UART_0_DEV UART2
93 #define UART_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART2_MASK))
94 #define UART_0_CLK UART_CLK
95 #define UART_0_IRQ_CHAN UART2_RX_TX_IRQn
96 #define UART_0_ISR isr_uart2_rx_tx
97 /* UART 0 pin configuration */
98 #define UART_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
99 #define UART_0_PORT PORTD
100 #define UART_0_RX_PIN 2
101 #define UART_0_TX_PIN 3
102 #define UART_0_AF 3
103 
104 /* UART 1 device configuration */
105 #define UART_1_DEV UART0
106 #define UART_1_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART0_MASK))
107 #define UART_1_CLK UART_CLK
108 #define UART_1_IRQ_CHAN UART0_RX_TX_IRQn
109 #define UART_1_ISR isr_uart0_rx_tx
110 /* UART 1 pin configuration */
111 #define UART_1_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
112 #define UART_1_PORT PORTD
113 #define UART_1_RX_PIN 6
114 #define UART_1_TX_PIN 7
115 #define UART_1_AF 3
116 
122 static const adc_conf_t adc_config[] = {
123  /* dev, pin, channel */
124  { ADC0, GPIO_PIN(PORT_E, 2), 1 },
125  { ADC0, GPIO_PIN(PORT_E, 3), 1 },
126  { ADC0, GPIO_PIN(PORT_D, 7), 22 },
127  { ADC0, GPIO_PIN(PORT_D, 5), 6 },
128  { ADC0, GPIO_PIN(PORT_E, 0), 10 },
129  { ADC0, GPIO_PIN(PORT_E, 1), 11 },
130 };
131 
132 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
133 
139 #define DAC_CONFIG {}
140 #define DAC_NUMOF 0
141 
147 static const pwm_conf_t pwm_config[] = {
148  {
149  .ftm = FTM0,
150  .chan = {
151  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 1 },
152  { .pin = GPIO_PIN(PORT_D, 4), .af = 4, .ftm_chan = 4 },
153  { .pin = GPIO_PIN(PORT_D, 6), .af = 4, .ftm_chan = 6 },
154  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 1 }
155  },
156  .chan_numof = 4,
157  .ftm_num = 0
158  }
159 };
160 
161 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
162 
175 static const uint32_t spi_clk_config[] = {
176  (
177  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
178  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
179  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
180  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
181  ),
182  (
183  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
184  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
185  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
186  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
187  ),
188  (
189  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
190  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
191  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
192  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
193  ),
194  (
195  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
196  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
197  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
198  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
199  ),
200  (
201  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
202  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
203  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
204  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
205  )
206 };
207 
208 static const spi_conf_t spi_config[] = {
209  {
210  .dev = SPI0,
211  .pin_miso = GPIO_PIN(PORT_C, 7),
212  .pin_mosi = GPIO_PIN(PORT_C, 6),
213  .pin_clk = GPIO_PIN(PORT_C, 5),
214  .pin_cs = {
215  GPIO_PIN(PORT_C, 4),
216  GPIO_UNDEF,
217  GPIO_UNDEF,
218  GPIO_UNDEF,
219  GPIO_UNDEF
220  },
221  .pcr = GPIO_AF_2,
222  .simmask = SIM_SCGC6_SPI0_MASK
223  },
224  {
225  .dev = SPI1,
226  .pin_miso = GPIO_PIN(PORT_B, 17),
227  .pin_mosi = GPIO_PIN(PORT_B, 16),
228  .pin_clk = GPIO_PIN(PORT_B, 11),
229  .pin_cs = {
230  GPIO_PIN(PORT_B, 10),
231  GPIO_UNDEF,
232  GPIO_UNDEF,
233  GPIO_UNDEF,
234  GPIO_UNDEF
235  },
236  .pcr = GPIO_AF_2,
237  .simmask = SIM_SCGC6_SPI1_MASK
238  }
239 };
240 
241 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
242 
249 #define I2C_NUMOF (1U)
250 #define I2C_CLK (48e6)
251 #define I2C_0_EN 1
252 #define I2C_IRQ_PRIO 1
253 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
254 #define KINETIS_I2C_F_ICR_LOW (0x3D)
255 #define KINETIS_I2C_F_MULT_LOW (2)
256 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
257 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
258 #define KINETIS_I2C_F_MULT_NORMAL (1)
259 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
260 #define KINETIS_I2C_F_ICR_FAST (0x17)
261 #define KINETIS_I2C_F_MULT_FAST (0)
262 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
263 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
264 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
265 
266 /* I2C 0 device configuration */
267 #define I2C_0_DEV I2C1
268 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
269 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
270 #define I2C_0_IRQ I2C1_IRQn
271 #define I2C_0_IRQ_HANDLER isr_i2c1
272 /* I2C 0 pin configuration */
273 #define I2C_0_PORT PORTE
274 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
275 #define I2C_0_PIN_AF 6
276 #define I2C_0_SDA_PIN 0
277 #define I2C_0_SCL_PIN 1
278 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
279 
287 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
288 
294 #define RTT_NUMOF (1U)
295 #define RTC_NUMOF (1U)
296 #define RTT_DEV RTC
297 #define RTT_IRQ RTC_IRQn
298 #define RTT_IRQ_PRIO 10
299 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
300 #define RTT_ISR isr_rtc
301 #define RTT_FREQUENCY (1)
302 #define RTT_MAX_VALUE (0xffffffff)
303 
309 #define KINETIS_RNGA RNG
310 #define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
311 #define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
312 
315 #ifdef __cplusplus
316 }
317 #endif
318 
319 #endif /* PERIPH_CONF_H */
320 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
use alternate function 2
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_ssi_t * dev
SSI device.