boards/pba-d-01-kw2x/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 #define KINETIS_CPU_USE_MCG 1
37 
38 #define KINETIS_MCG_USE_ERC 1
39 #define KINETIS_MCG_USE_PLL 1
40 #define KINETIS_MCG_DCO_RANGE (24000000U)
41 #define KINETIS_MCG_ERC_OSCILLATOR 0
42 #define KINETIS_MCG_ERC_FRDIV 2
43 #define KINETIS_MCG_ERC_RANGE 1
44 #define KINETIS_MCG_ERC_FREQ 4000000
45 #define KINETIS_MCG_PLL_PRDIV 1
46 #define KINETIS_MCG_PLL_VDIV0 0
47 #define KINETIS_MCG_PLL_FREQ 48000000
48 
49 #define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
50 #define CLOCK_BUSCLOCK CLOCK_CORECLOCK
51 
57 #define PIT_NUMOF (2U)
58 #define PIT_CONFIG { \
59  { \
60  .prescaler_ch = 0, \
61  .count_ch = 1, \
62  }, \
63  { \
64  .prescaler_ch = 2, \
65  .count_ch = 3, \
66  }, \
67  }
68 #define LPTMR_NUMOF (0U)
69 #define LPTMR_CONFIG {}
70 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
71 
72 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
73 #define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
74 #define PIT_ISR_0 isr_pit1
75 #define PIT_ISR_1 isr_pit3
76 #define LPTMR_ISR_0 isr_lptmr0
77 
84 static const uart_conf_t uart_config[] = {
85  {
86  .dev = UART2,
87  .clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART2_SHIFT)),
88  .freq = CLOCK_BUSCLOCK,
89  .pin_rx = GPIO_PIN(PORT_D, 2),
90  .pin_tx = GPIO_PIN(PORT_D, 3),
91  .pcr_rx = PORT_PCR_MUX(3),
92  .pcr_tx = PORT_PCR_MUX(3),
93  .irqn = UART2_RX_TX_IRQn,
94  },
95  {
96  .dev = UART0,
97  .clken = (volatile uint32_t*)(BITBAND_REGADDR(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT)),
98  .freq = CLOCK_CORECLOCK,
99  .pin_rx = GPIO_PIN(PORT_D, 6),
100  .pin_tx = GPIO_PIN(PORT_D, 7),
101  .pcr_rx = PORT_PCR_MUX(3),
102  .pcr_tx = PORT_PCR_MUX(3),
103  .irqn = UART0_RX_TX_IRQn,
104  }
105 };
106 
107 #define UART_0_ISR (isr_uart2_rx_tx)
108 #define UART_1_ISR (isr_uart0_rx_tx)
109 
110 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
111 
117 static const adc_conf_t adc_config[] = {
118  /* dev, pin, channel */
119  { ADC0, GPIO_PIN(PORT_E, 2), 1 },
120  { ADC0, GPIO_PIN(PORT_E, 3), 1 },
121  { ADC0, GPIO_PIN(PORT_D, 7), 22 },
122  { ADC0, GPIO_PIN(PORT_D, 5), 6 },
123  { ADC0, GPIO_PIN(PORT_E, 0), 10 },
124  { ADC0, GPIO_PIN(PORT_E, 1), 11 },
125 };
126 
127 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
128 
134 #define DAC_CONFIG {}
135 #define DAC_NUMOF 0
136 
142 static const pwm_conf_t pwm_config[] = {
143  {
144  .ftm = FTM0,
145  .chan = {
146  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 1 },
147  { .pin = GPIO_PIN(PORT_D, 4), .af = 4, .ftm_chan = 4 },
148  { .pin = GPIO_PIN(PORT_D, 6), .af = 4, .ftm_chan = 6 },
149  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 1 }
150  },
151  .chan_numof = 4,
152  .ftm_num = 0
153  }
154 };
155 
156 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
157 
170 static const uint32_t spi_clk_config[] = {
171  (
172  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
173  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
174  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
175  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
176  ),
177  (
178  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
179  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
180  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
181  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
182  ),
183  (
184  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
185  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
186  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
187  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
188  ),
189  (
190  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
191  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
192  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
193  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
194  ),
195  (
196  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
197  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
198  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
199  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
200  )
201 };
202 
203 static const spi_conf_t spi_config[] = {
204  {
205  .dev = SPI0,
206  .pin_miso = GPIO_PIN(PORT_C, 7),
207  .pin_mosi = GPIO_PIN(PORT_C, 6),
208  .pin_clk = GPIO_PIN(PORT_C, 5),
209  .pin_cs = {
210  GPIO_PIN(PORT_C, 4),
211  GPIO_UNDEF,
212  GPIO_UNDEF,
213  GPIO_UNDEF,
214  GPIO_UNDEF
215  },
216  .pcr = GPIO_AF_2,
217  .simmask = SIM_SCGC6_SPI0_MASK
218  },
219  {
220  .dev = SPI1,
221  .pin_miso = GPIO_PIN(PORT_B, 17),
222  .pin_mosi = GPIO_PIN(PORT_B, 16),
223  .pin_clk = GPIO_PIN(PORT_B, 11),
224  .pin_cs = {
225  GPIO_PIN(PORT_B, 10),
226  GPIO_UNDEF,
227  GPIO_UNDEF,
228  GPIO_UNDEF,
229  GPIO_UNDEF
230  },
231  .pcr = GPIO_AF_2,
232  .simmask = SIM_SCGC6_SPI1_MASK
233  }
234 };
235 
236 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
237 
244 #define I2C_NUMOF (1U)
245 #define I2C_CLK (48e6)
246 #define I2C_0_EN 1
247 #define I2C_IRQ_PRIO 1
248 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
249 #define KINETIS_I2C_F_ICR_LOW (0x3D)
250 #define KINETIS_I2C_F_MULT_LOW (2)
251 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
252 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
253 #define KINETIS_I2C_F_MULT_NORMAL (1)
254 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
255 #define KINETIS_I2C_F_ICR_FAST (0x17)
256 #define KINETIS_I2C_F_MULT_FAST (0)
257 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
258 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
259 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
260 
261 /* I2C 0 device configuration */
262 #define I2C_0_DEV I2C1
263 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
264 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
265 #define I2C_0_IRQ I2C1_IRQn
266 #define I2C_0_IRQ_HANDLER isr_i2c1
267 /* I2C 0 pin configuration */
268 #define I2C_0_PORT PORTE
269 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
270 #define I2C_0_PIN_AF 6
271 #define I2C_0_SDA_PIN 0
272 #define I2C_0_SCL_PIN 1
273 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
274 
282 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
283 
289 #define RTT_NUMOF (1U)
290 #define RTC_NUMOF (1U)
291 #define RTT_DEV RTC
292 #define RTT_IRQ RTC_IRQn
293 #define RTT_IRQ_PRIO 10
294 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
295 #define RTT_ISR isr_rtc
296 #define RTT_FREQUENCY (1)
297 #define RTT_MAX_VALUE (0xffffffff)
298 
304 #define KINETIS_RNGA RNG
305 #define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
306 #define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
307 
310 #ifdef __cplusplus
311 }
312 #endif
313 
314 #endif /* PERIPH_CONF_H */
315 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
use alternate function 2
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_ssi_t * dev
SSI device.