boards/pba-d-01-kw2x/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 static const clock_config_t clock_config = {
37  /*
38  * This configuration results in the system running from the PLL output with
39  * the following clock frequencies:
40  * Core: 48 MHz
41  * Bus: 48 MHz
42  * Flash: 24 MHz
43  */
44  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
45  SIM_CLKDIV1_OUTDIV4(1),
46  .default_mode = KINETIS_MCG_MODE_PEE,
47  /* The modem generates a 4 MHz clock signal */
48  .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
49  .fcrdiv = 0, /* Fast IRC divide by 1 => 4 MHz */
50  .oscsel = 0, /* Use EXTAL0 for external clock */
51  .clc = 0, /* OSC0 is unused*/
52  .fll_frdiv = 0b010, /* Divide by 128 */
53  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
54  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1280, /* FLL freq = 40 MHz */
55  .pll_prdiv = 0b00001, /* Divide by 2 */
56  .pll_vdiv = 0b00000, /* Multiply by 24 => PLL freq = 48 MHz */
57  .enable_oscillator = false, /* Use modem clock from EXTAL0 */
58  .select_fast_irc = true,
59  .enable_mcgirclk = false,
60 };
61 #define CLOCK_CORECLOCK (48000000ul)
62 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
63 
69 #define PIT_NUMOF (2U)
70 #define PIT_CONFIG { \
71  { \
72  .prescaler_ch = 0, \
73  .count_ch = 1, \
74  }, \
75  { \
76  .prescaler_ch = 2, \
77  .count_ch = 3, \
78  }, \
79  }
80 #define LPTMR_NUMOF (0U)
81 #define LPTMR_CONFIG {}
82 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
83 
84 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
85 #define PIT_ISR_0 isr_pit1
86 #define PIT_ISR_1 isr_pit3
87 #define LPTMR_ISR_0 isr_lptmr0
88 
95 static const uart_conf_t uart_config[] = {
96  {
97  .dev = UART2,
98  .freq = CLOCK_BUSCLOCK,
99  .pin_rx = GPIO_PIN(PORT_D, 2),
100  .pin_tx = GPIO_PIN(PORT_D, 3),
101  .pcr_rx = PORT_PCR_MUX(3),
102  .pcr_tx = PORT_PCR_MUX(3),
103  .irqn = UART2_RX_TX_IRQn,
104  .scgc_addr = &SIM->SCGC4,
105  .scgc_bit = SIM_SCGC4_UART2_SHIFT,
106  .mode = UART_MODE_8N1
107  },
108  {
109  .dev = UART0,
110  .freq = CLOCK_CORECLOCK,
111  .pin_rx = GPIO_PIN(PORT_D, 6),
112  .pin_tx = GPIO_PIN(PORT_D, 7),
113  .pcr_rx = PORT_PCR_MUX(3),
114  .pcr_tx = PORT_PCR_MUX(3),
115  .irqn = UART0_RX_TX_IRQn,
116  .scgc_addr = &SIM->SCGC4,
117  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
118  .mode = UART_MODE_8N1
119  }
120 };
121 
122 #define UART_0_ISR (isr_uart2_rx_tx)
123 #define UART_1_ISR (isr_uart0_rx_tx)
124 
125 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
126 
132 static const adc_conf_t adc_config[] = {
133  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 2), .chan = 1 },
134  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 3), .chan = 1 },
135  { .dev = ADC0, .pin = GPIO_PIN(PORT_D, 7), .chan = 22 },
136  { .dev = ADC0, .pin = GPIO_PIN(PORT_D, 5), .chan = 6 },
137  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 0), .chan = 10 },
138  { .dev = ADC0, .pin = GPIO_PIN(PORT_E, 1), .chan = 11 }
139 };
140 
141 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
142 
148 static const pwm_conf_t pwm_config[] = {
149  {
150  .ftm = FTM0,
151  .chan = {
152  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 1 },
153  { .pin = GPIO_PIN(PORT_D, 4), .af = 4, .ftm_chan = 4 },
154  { .pin = GPIO_PIN(PORT_D, 6), .af = 4, .ftm_chan = 6 },
155  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 1 }
156  },
157  .chan_numof = 4,
158  .ftm_num = 0
159  }
160 };
161 
162 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
163 
176 static const uint32_t spi_clk_config[] = {
177  (
178  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
179  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
180  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
181  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
182  ),
183  (
184  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
185  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
186  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
187  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
188  ),
189  (
190  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
191  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
192  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
193  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
194  ),
195  (
196  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
197  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
198  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
199  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
200  ),
201  (
202  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
203  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
204  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
205  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
206  )
207 };
208 
209 static const spi_conf_t spi_config[] = {
210  {
211  .dev = SPI0,
212  .pin_miso = GPIO_PIN(PORT_C, 7),
213  .pin_mosi = GPIO_PIN(PORT_C, 6),
214  .pin_clk = GPIO_PIN(PORT_C, 5),
215  .pin_cs = {
216  GPIO_PIN(PORT_C, 4),
217  GPIO_UNDEF,
218  GPIO_UNDEF,
219  GPIO_UNDEF,
220  GPIO_UNDEF
221  },
222  .pcr = GPIO_AF_2,
223  .simmask = SIM_SCGC6_SPI0_MASK
224  },
225  {
226  .dev = SPI1,
227  .pin_miso = GPIO_PIN(PORT_B, 17),
228  .pin_mosi = GPIO_PIN(PORT_B, 16),
229  .pin_clk = GPIO_PIN(PORT_B, 11),
230  .pin_cs = {
231  GPIO_PIN(PORT_B, 10),
232  GPIO_UNDEF,
233  GPIO_UNDEF,
234  GPIO_UNDEF,
235  GPIO_UNDEF
236  },
237  .pcr = GPIO_AF_2,
238  .simmask = SIM_SCGC6_SPI1_MASK
239  }
240 };
241 
242 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
243 
250 #define I2C_NUMOF (1U)
251 #define I2C_0_EN 1
252 /* Low (10 kHz): MUL = 2, SCL divider = 2560, total: 5120 */
253 #define KINETIS_I2C_F_ICR_LOW (0x3D)
254 #define KINETIS_I2C_F_MULT_LOW (1)
255 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
256 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
257 #define KINETIS_I2C_F_MULT_NORMAL (1)
258 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
259 #define KINETIS_I2C_F_ICR_FAST (0x17)
260 #define KINETIS_I2C_F_MULT_FAST (0)
261 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
262 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
263 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
264 
265 /* I2C 0 device configuration */
266 #define I2C_0_DEV I2C1
267 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
268 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
269 #define I2C_0_IRQ I2C1_IRQn
270 #define I2C_0_IRQ_HANDLER isr_i2c1
271 /* I2C 0 pin configuration */
272 #define I2C_0_PORT PORTE
273 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
274 #define I2C_0_PIN_AF 6
275 #define I2C_0_SDA_PIN 0
276 #define I2C_0_SCL_PIN 1
277 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
278 
285 #define RTT_NUMOF (1U)
286 #define RTC_NUMOF (1U)
287 #define RTT_DEV RTC
288 #define RTT_IRQ RTC_IRQn
289 #define RTT_IRQ_PRIO 10
290 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
291 #define RTT_ISR isr_rtc
292 #define RTT_FREQUENCY (1)
293 #define RTT_MAX_VALUE (0xffffffff)
294 
300 #define KINETIS_RNGA RNG
301 #define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
302 #define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
303 
306 #ifdef __cplusplus
307 }
308 #endif
309 
310 #endif /* PERIPH_CONF_H */
311 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
uint32_t clkdiv1
Clock divider bitfield setting, see reference manual for SIM_CLKDIV1.
ADC_Type * dev
ADC device.
use alternate function 2
#define UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Clock configuration for Kinetis CPUs.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
CPU specific ADC configuration.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
cc2538_ssi_t * dev
SSI device.