boards/pba-d-01-kw2x/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C"
29 {
30 #endif
31 
36 #define KINETIS_CPU_USE_MCG 1
37 
38 #define KINETIS_MCG_USE_ERC 1
39 #define KINETIS_MCG_USE_PLL 1
40 #define KINETIS_MCG_DCO_RANGE (24000000U)
41 #define KINETIS_MCG_ERC_OSCILLATOR 0
42 #define KINETIS_MCG_ERC_FRDIV 2
43 #define KINETIS_MCG_ERC_RANGE 1
44 #define KINETIS_MCG_ERC_FREQ 4000000
45 #define KINETIS_MCG_PLL_PRDIV 1
46 #define KINETIS_MCG_PLL_VDIV0 0
47 #define KINETIS_MCG_PLL_FREQ 48000000
48 
49 #define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
50 #define CLOCK_BUSCLOCK CLOCK_CORECLOCK
51 
57 #define PIT_NUMOF (2U)
58 #define PIT_CONFIG { \
59  { \
60  .prescaler_ch = 0, \
61  .count_ch = 1, \
62  }, \
63  { \
64  .prescaler_ch = 2, \
65  .count_ch = 3, \
66  }, \
67  }
68 #define LPTMR_NUMOF (0U)
69 #define LPTMR_CONFIG {}
70 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
71 
72 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
73 #define PIT_ISR_0 isr_pit1
74 #define PIT_ISR_1 isr_pit3
75 #define LPTMR_ISR_0 isr_lptmr0
76 
83 static const uart_conf_t uart_config[] = {
84  {
85  .dev = UART2,
86  .freq = CLOCK_BUSCLOCK,
87  .pin_rx = GPIO_PIN(PORT_D, 2),
88  .pin_tx = GPIO_PIN(PORT_D, 3),
89  .pcr_rx = PORT_PCR_MUX(3),
90  .pcr_tx = PORT_PCR_MUX(3),
91  .irqn = UART2_RX_TX_IRQn,
92  .scgc_addr = &SIM->SCGC4,
93  .scgc_bit = SIM_SCGC4_UART2_SHIFT,
94  .mode = UART_MODE_8N1
95  },
96  {
97  .dev = UART0,
98  .freq = CLOCK_CORECLOCK,
99  .pin_rx = GPIO_PIN(PORT_D, 6),
100  .pin_tx = GPIO_PIN(PORT_D, 7),
101  .pcr_rx = PORT_PCR_MUX(3),
102  .pcr_tx = PORT_PCR_MUX(3),
103  .irqn = UART0_RX_TX_IRQn,
104  .scgc_addr = &SIM->SCGC4,
105  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
106  .mode = UART_MODE_8N1
107  }
108 };
109 
110 #define UART_0_ISR (isr_uart2_rx_tx)
111 #define UART_1_ISR (isr_uart0_rx_tx)
112 
113 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
114 
120 static const adc_conf_t adc_config[] = {
121  /* dev, pin, channel */
122  { ADC0, GPIO_PIN(PORT_E, 2), 1 },
123  { ADC0, GPIO_PIN(PORT_E, 3), 1 },
124  { ADC0, GPIO_PIN(PORT_D, 7), 22 },
125  { ADC0, GPIO_PIN(PORT_D, 5), 6 },
126  { ADC0, GPIO_PIN(PORT_E, 0), 10 },
127  { ADC0, GPIO_PIN(PORT_E, 1), 11 },
128 };
129 
130 #define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
131 
137 #define DAC_CONFIG {}
138 #define DAC_NUMOF 0
139 
145 static const pwm_conf_t pwm_config[] = {
146  {
147  .ftm = FTM0,
148  .chan = {
149  { .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 1 },
150  { .pin = GPIO_PIN(PORT_D, 4), .af = 4, .ftm_chan = 4 },
151  { .pin = GPIO_PIN(PORT_D, 6), .af = 4, .ftm_chan = 6 },
152  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 1 }
153  },
154  .chan_numof = 4,
155  .ftm_num = 0
156  }
157 };
158 
159 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
160 
173 static const uint32_t spi_clk_config[] = {
174  (
175  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
176  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
177  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
178  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
179  ),
180  (
181  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
182  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
183  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
184  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
185  ),
186  (
187  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
188  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
189  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
190  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
191  ),
192  (
193  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
194  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
195  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
196  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
197  ),
198  (
199  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
200  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
201  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
202  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
203  )
204 };
205 
206 static const spi_conf_t spi_config[] = {
207  {
208  .dev = SPI0,
209  .pin_miso = GPIO_PIN(PORT_C, 7),
210  .pin_mosi = GPIO_PIN(PORT_C, 6),
211  .pin_clk = GPIO_PIN(PORT_C, 5),
212  .pin_cs = {
213  GPIO_PIN(PORT_C, 4),
214  GPIO_UNDEF,
215  GPIO_UNDEF,
216  GPIO_UNDEF,
217  GPIO_UNDEF
218  },
219  .pcr = GPIO_AF_2,
220  .simmask = SIM_SCGC6_SPI0_MASK
221  },
222  {
223  .dev = SPI1,
224  .pin_miso = GPIO_PIN(PORT_B, 17),
225  .pin_mosi = GPIO_PIN(PORT_B, 16),
226  .pin_clk = GPIO_PIN(PORT_B, 11),
227  .pin_cs = {
228  GPIO_PIN(PORT_B, 10),
229  GPIO_UNDEF,
230  GPIO_UNDEF,
231  GPIO_UNDEF,
232  GPIO_UNDEF
233  },
234  .pcr = GPIO_AF_2,
235  .simmask = SIM_SCGC6_SPI1_MASK
236  }
237 };
238 
239 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
240 
247 #define I2C_NUMOF (1U)
248 #define I2C_CLK (48e6)
249 #define I2C_0_EN 1
250 #define I2C_IRQ_PRIO 1
251 /* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
252 #define KINETIS_I2C_F_ICR_LOW (0x3D)
253 #define KINETIS_I2C_F_MULT_LOW (2)
254 /* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
255 #define KINETIS_I2C_F_ICR_NORMAL (0x1F)
256 #define KINETIS_I2C_F_MULT_NORMAL (1)
257 /* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
258 #define KINETIS_I2C_F_ICR_FAST (0x17)
259 #define KINETIS_I2C_F_MULT_FAST (0)
260 /* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
261 #define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
262 #define KINETIS_I2C_F_MULT_FAST_PLUS (0)
263 
264 /* I2C 0 device configuration */
265 #define I2C_0_DEV I2C1
266 #define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
267 #define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
268 #define I2C_0_IRQ I2C1_IRQn
269 #define I2C_0_IRQ_HANDLER isr_i2c1
270 /* I2C 0 pin configuration */
271 #define I2C_0_PORT PORTE
272 #define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
273 #define I2C_0_PIN_AF 6
274 #define I2C_0_SDA_PIN 0
275 #define I2C_0_SCL_PIN 1
276 #define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
277 
285 #define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
286 
292 #define RTT_NUMOF (1U)
293 #define RTC_NUMOF (1U)
294 #define RTT_DEV RTC
295 #define RTT_IRQ RTC_IRQn
296 #define RTT_IRQ_PRIO 10
297 #define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
298 #define RTT_ISR isr_rtc
299 #define RTT_FREQUENCY (1)
300 #define RTT_MAX_VALUE (0xffffffff)
301 
307 #define KINETIS_RNGA RNG
308 #define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
309 #define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
310 
313 #ifdef __cplusplus
314 }
315 #endif
316 
317 #endif /* PERIPH_CONF_H */
318 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
cc2538_uart_t *const UART0
UART0 Instance.
PWM configuration structure.
use alternate function 2
#define UART_MODE_8N1
8 data bits, no parity, 1 stop bit
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
CPU specific ADC configuration.
cc2538_ssi_t * dev
SSI device.