periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2017-2018 Eistec AB
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdbool.h>
26 
27 #include "cpu.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 #ifdef PORT_PCR_MUX
34 # define KINETIS_HAVE_PCR
35 #endif
36 
37 #ifdef SIM_PINSEL_REG
38 # define KINETIS_HAVE_PINSEL
39 #endif
40 
41 #ifdef ADC_CFG1_MODE_MASK
42 # define KINETIS_HAVE_ADC_K
43 #endif
44 
45 #ifdef SPI_CTAR_CPHA_MASK
46 # define KINETIS_HAVE_MK_SPI
47 #endif
48 
49 #ifdef LPTMR_CSR_TEN_MASK
50 # define KINETIS_HAVE_LPTMR
51 #endif
52 
57 #define HAVE_GPIO_T
58 typedef uint16_t gpio_t;
64 #define GPIO_UNDEF (0xffff)
65 
69 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
70 
71 #ifdef SIM_UIDH_UID_MASK
72 /* Kinetis Cortex-M4 has a 128 bit SIM UID */
76 #define CPUID_ADDR (&SIM->UIDH)
77 
81 #define CPUID_LEN (16U)
82 #else /* defined(SIM_UIDH_UID_MASK) */
83 /* Kinetis Cortex-M0+ has a 96 bit SIM UID */
87 #define CPUID_ADDR (&SIM->UIDMH)
88 
91 #define CPUID_LEN (12U)
92 #endif /* defined(SIM_UIDH_UID_MASK) */
93 
103 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
104 
111 #define SPI_HWCS(x) (x)
112 
116 #define SPI_HWCS_NUMOF (5)
117 
122 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
123 #define PERIPH_SPI_NEEDS_TRANSFER_REG 1
124 #define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
125 
130 #define PERIPH_TIMER_PROVIDES_SET
131 
135 #define PM_NUM_MODES (1U)
136 
137 #ifdef RTC
138 /* All Kinetis CPUs have exactly one RTC hardware module, except for the KL02
139  * family which don't have an RTC at all */
144 #define RTT_FREQUENCY (1)
145 #define RTT_MAX_VALUE (0xffffffff)
146 
147 #endif
148 
149 #ifndef DOXYGEN
150 
154 #define HAVE_GPIO_MODE_T
155 typedef enum {
156  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
157  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
158  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
159  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
160  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
161  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
162 } gpio_mode_t;
164 #endif /* ndef DOXYGEN */
165 
166 #ifdef KINETIS_HAVE_PCR
167 
172 typedef enum {
173  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
174  GPIO_AF_GPIO = PORT_PCR_MUX(1),
175  GPIO_AF_2 = PORT_PCR_MUX(2),
176  GPIO_AF_3 = PORT_PCR_MUX(3),
177  GPIO_AF_4 = PORT_PCR_MUX(4),
178  GPIO_AF_5 = PORT_PCR_MUX(5),
179  GPIO_AF_6 = PORT_PCR_MUX(6),
180  GPIO_AF_7 = PORT_PCR_MUX(7),
181 #ifdef PORT_PCR_ODE_MASK
182  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
183 #endif
184  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
185  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
186 } gpio_pcr_t;
187 #endif /* KINETIS_HAVE_PCR */
188 
189 #ifndef DOXYGEN
190 
194 #ifdef KINETIS_HAVE_PCR
195 #define HAVE_GPIO_FLANK_T
196 typedef enum {
197  GPIO_RISING = PORT_PCR_IRQC(0x9),
198  GPIO_FALLING = PORT_PCR_IRQC(0xa),
199  GPIO_BOTH = PORT_PCR_IRQC(0xb),
200 } gpio_flank_t;
201 #endif /* KINETIS_HAVE_PCR */
202 
203 #endif /* ndef DOXYGEN */
204 
210 enum {
211  PORT_A = 0,
212  PORT_B = 1,
213  PORT_C = 2,
214  PORT_D = 3,
215  PORT_E = 4,
216  PORT_F = 5,
217  PORT_G = 6,
219 };
220 
221 #ifndef DOXYGEN
222 
226 #define HAVE_ADC_RES_T
227 #ifdef KINETIS_HAVE_ADC_K
228 typedef enum {
229  ADC_RES_6BIT = (0xfe),
230  ADC_RES_8BIT = ADC_CFG1_MODE(0),
231  ADC_RES_10BIT = ADC_CFG1_MODE(2),
232  ADC_RES_12BIT = ADC_CFG1_MODE(1),
233  ADC_RES_14BIT = (0xff),
234  ADC_RES_16BIT = ADC_CFG1_MODE(3)
235 } adc_res_t;
236 #endif /* KINETIS_HAVE_ADC_K */
237 
239 #if defined(FTM_CnSC_MSB_MASK)
240 
243 #define PWM_CHAN_MAX (4U)
244 
249 #define HAVE_PWM_MODE_T
250 typedef enum {
251  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
252  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
253  PWM_CENTER = (FTM_CnSC_MSB_MASK)
254 } pwm_mode_t;
255 #endif /* defined(FTM_CnSC_MSB_MASK) */
256 #endif /* ndef DOXYGEN */
257 
261 typedef enum {
265 #if defined(UART_C1_M_MASK) || DOXYGEN
266  /* LPUART and UART mode bits coincide, so the same setting for UART works on
267  * the LPUART as well */
268  UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
269 #elif defined(LPUART_CTRL_M_MASK)
270  /* For CPUs which only have the LPUART */
271  UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
272 #endif
274 #if defined(UART_C1_M_MASK) || DOXYGEN
275  UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
276 #elif defined(LPUART_CTRL_M_MASK)
277  /* For CPUs which only have the LPUART */
278  UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
279 #endif
280 } uart_mode_t;
281 
282 #ifndef DOXYGEN
283 
288 #ifdef KINETIS_HAVE_MK_SPI
289 #define HAVE_SPI_MODE_T
290 typedef enum {
291  SPI_MODE_0 = 0,
292  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
293  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
294  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
295 } spi_mode_t;
297 #endif /* KINETIS_HAVE_MK_SPI */
298 #endif /* ndef DOXYGEN */
299 
303 typedef struct {
307  ADC_Type *dev;
313  gpio_t pin;
320  uint8_t chan;
326  uint8_t avg;
327 } adc_conf_t;
328 
332 #define ADC_AVG_NONE (0)
333 
336 #define ADC_AVG_MAX (ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3))
337 
338 #if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
339 
342 typedef struct {
343  DAC_Type *dev;
344  volatile uint32_t *scgc_addr;
345  uint8_t scgc_bit;
346 } dac_conf_t;
347 #endif
348 
352 typedef struct {
354  uint8_t prescaler_ch;
356  uint8_t count_ch;
357 } pit_conf_t;
358 
359 #ifdef KINETIS_HAVE_LPTMR
360 
363 typedef struct {
365  LPTMR_Type *dev;
367  uint32_t base_freq;
369  uint8_t src;
371  uint8_t irqn;
372 } lptmr_conf_t;
373 #endif /* KINETIS_HAVE_LPTMR */
374 
375 #ifdef FTM_CnSC_MSB_MASK
376 
379 typedef struct {
380  FTM_Type* ftm;
381  struct {
382  gpio_t pin;
383  uint8_t af;
384  uint8_t ftm_chan;
385  } chan[PWM_CHAN_MAX];
386  uint8_t chan_numof;
387  uint8_t ftm_num;
388 #ifdef KINETIS_HAVE_PINSEL
389  volatile uint32_t *pinsel;
390  uint32_t pinsel_mask;
391  uint32_t pinsel_val;
392 #endif
393 } pwm_conf_t;
394 #endif
395 
396 #ifndef DOXYGEN
397 #define HAVE_I2C_SPEED_T
398 typedef enum {
399  I2C_SPEED_LOW = 10000ul,
400  I2C_SPEED_NORMAL = 100000ul,
401  I2C_SPEED_FAST = 400000ul,
402  I2C_SPEED_FAST_PLUS = 1000000ul,
403  /* High speed is not supported without external hardware hacks */
404  I2C_SPEED_HIGH = 3400000ul,
405 } i2c_speed_t;
410 #define PERIPH_I2C_NEED_READ_REG
411 #define PERIPH_I2C_NEED_READ_REGS
412 #define PERIPH_I2C_NEED_WRITE_REG
413 #define PERIPH_I2C_NEED_WRITE_REGS
414 
415 #endif /* !defined(DOXYGEN) */
416 
420 typedef struct {
421  I2C_Type *i2c;
422  gpio_t scl_pin;
423  gpio_t sda_pin;
424  uint32_t freq;
425  i2c_speed_t speed;
427  uint32_t scl_pcr;
428  uint32_t sda_pcr;
429 } i2c_conf_t;
430 
434 typedef struct {
435  SPI_Type *dev;
436  gpio_t pin_miso;
437  gpio_t pin_mosi;
438  gpio_t pin_clk;
439  gpio_t pin_cs[SPI_HWCS_NUMOF];
440 #ifdef KINETIS_HAVE_PCR
441  gpio_pcr_t pcr;
442 #endif /* KINETIS_HAVE_PCR */
443 #ifdef KINETIS_HAVE_PINSEL
444  volatile uint32_t *pinsel;
445  uint32_t pinsel_mask;
446  uint32_t pinsel_val;
447 #endif
448  uint32_t simmask;
449 } spi_conf_t;
450 
454 enum {
456 #ifdef KINETIS_HAVE_LPTMR
457  TIMER_LPTMR,
458 #endif /* KINETIS_HAVE_LPTMR */
459 };
460 
466 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
467 #ifdef KINETIS_HAVE_LPTMR
468 
469 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
470 #endif /* KINETIS_HAVE_LPTMR */
471 
476 typedef enum {
479 } uart_type_t;
480 
484 typedef struct {
485  void *dev;
486  uint32_t freq;
487  gpio_t pin_rx;
488  gpio_t pin_tx;
489 #ifdef KINETIS_HAVE_PCR
490  uint32_t pcr_rx;
491  uint32_t pcr_tx;
492 #endif
493 #ifdef KINETIS_HAVE_PINSEL
494  volatile uint32_t *pinsel;
495  uint32_t pinsel_mask;
496  uint32_t pinsel_val;
497 #endif
499  volatile uint32_t *scgc_addr;
500  uint8_t scgc_bit;
502  uart_type_t type;
503 } uart_conf_t;
504 
505 #if !defined(KINETIS_HAVE_PLL)
506 #if defined(MCG_C6_PLLS_MASK) || DOXYGEN
507 
510 #define KINETIS_HAVE_PLL 1
511 #else
512 #define KINETIS_HAVE_PLL 0
513 #endif
514 #endif /* !defined(KINETIS_HAVE_PLL) */
515 
516 #ifdef MODULE_PERIPH_MCG
517 
520 typedef enum kinetis_mcg_mode {
521  KINETIS_MCG_MODE_FEI = 0,
522  KINETIS_MCG_MODE_FEE = 1,
523  KINETIS_MCG_MODE_FBI = 2,
524  KINETIS_MCG_MODE_FBE = 3,
525  KINETIS_MCG_MODE_BLPI = 4,
526  KINETIS_MCG_MODE_BLPE = 5,
527 #if KINETIS_HAVE_PLL
528  KINETIS_MCG_MODE_PBE = 6,
529  KINETIS_MCG_MODE_PEE = 7,
530 #endif
531  KINETIS_MCG_MODE_NUMOF,
532 } kinetis_mcg_mode_t;
533 
537 typedef enum {
539  KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
541  KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
543  KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
545  KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
547  KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
549  KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
551  KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
553  KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
554 } kinetis_mcg_fll_t;
555 
559 typedef enum {
560  KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
561  KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
562  KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
563 } kinetis_mcg_erc_range_t;
564 
571 typedef enum {
580  KINETIS_CLOCK_OSC0_EN = (1 << 0),
589  KINETIS_CLOCK_RTCOSC_EN = (1 << 1),
604  KINETIS_CLOCK_USE_FAST_IRC = (1 << 2),
613  KINETIS_CLOCK_MCGIRCLK_EN = (1 << 3),
624  KINETIS_CLOCK_MCGIRCLK_STOP_EN = (1 << 4),
625 } kinetis_clock_flags_t;
626 
630 typedef struct {
640  uint32_t clkdiv1;
652  uint32_t rtc_clc;
666  uint32_t osc32ksel;
672  unsigned int clock_flags;
678  kinetis_mcg_mode_t default_mode;
684  kinetis_mcg_erc_range_t erc_range;
695  uint8_t osc_clc;
705  uint8_t oscsel;
715  uint8_t fcrdiv;
725  uint8_t fll_frdiv;
732  kinetis_mcg_fll_t fll_factor_fei;
739  kinetis_mcg_fll_t fll_factor_fee;
740 #if KINETIS_HAVE_PLL
741 
750  uint8_t pll_prdiv;
760  uint8_t pll_vdiv;
761 #endif /* KINETIS_HAVE_PLL */
762 } clock_config_t;
763 #endif /* MODULE_PERIPH_MCG */
764 
770 void gpio_init_port(gpio_t pin, uint32_t pcr);
771 
772 #ifdef __cplusplus
773 }
774 #endif
775 
776 #endif /* PERIPH_CPU_H */
777 
port C
Definition: periph_cpu.h:38
fast mode: ~400 kbit/s
Definition: i2c.h:184
CPOL=0, CPHA=1.
Definition: spi.h:159
configure as output in push-pull mode
Definition: gpio.h:117
high speed mode: ~3400 kbit/s
Definition: i2c.h:186
I2C configuration options.
Definition: periph_cpu.h:128
not supported
Definition: periph_cpu.h:144
emit interrupt on rising flank
Definition: gpio.h:131
IRQn_Type irqn
IRQ number for this module.
Definition: periph_cpu.h:498
ADC resolution: 12 bit.
Definition: adc.h:97
gpio_t pin_tx
TX pin.
Definition: periph_cpu.h:488
uint8_t avg
Hardware averaging configuration.
Definition: periph_cpu.h:326
CPU specific timer PIT module configuration.
Definition: periph_cpu.h:352
Kinetis Low-power UART (LPUART) module type.
Definition: periph_cpu.h:478
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:93
uint8_t prescaler_ch
Prescaler channel.
Definition: periph_cpu.h:354
gpio_t pin_miso
MISO pin used.
Definition: periph_cpu.h:436
enum IRQn IRQn_Type
Interrupt Number Definition.
CPOL=0, CPHA=0.
Definition: spi.h:158
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:435
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:181
overall number of available ports
Definition: periph_cpu.h:218
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
Definition: periph_cpu.h:486
uint8_t chan
ADC channel.
Definition: periph_cpu.h:320
PWM device configuration.
uart_type_t type
Hardware module type (KINETIS_UART or KINETIS_LPUART)
Definition: periph_cpu.h:502
emit interrupt on both flanks
Definition: gpio.h:132
uart_mode_t
UART transmission modes.
Definition: periph_cpu.h:261
port F
Definition: periph_cpu.h:41
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:129
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
8 data bits, no parity, 1 stop bit
Definition: periph_cpu.h:263
ADC resolution: 14 bit.
Definition: adc.h:98
left aligned PWM
Definition: periph_cpu.h:142
ADC resolution: 10 bit.
Definition: adc.h:96
CPOL=1, CPHA=1.
Definition: spi.h:161
uint32_t sda_pcr
PORT module PCR setting for the SDA pin.
Definition: periph_cpu.h:428
port E
Definition: periph_cpu.h:40
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
gpio_t adc_conf_t
ADC configuration wrapper.
Definition: periph_cpu.h:313
gpio_t pin_clk
CLK pin used.
Definition: periph_cpu.h:438
port D
Definition: periph_cpu.h:39
uint32_t freq
I2C module clock frequency, usually CLOCK_BUSCLOCK or CLOCK_CORECLOCK.
Definition: periph_cpu.h:424
ADC resolution: 16 bit.
Definition: adc.h:99
PIT.
Definition: periph_cpu.h:455
port A
Definition: periph_cpu.h:36
ADC resolution: 8 bit.
Definition: adc.h:95
uint32_t scl_pcr
PORT module PCR setting for the SCL pin.
Definition: periph_cpu.h:427
ADC resolution: 6 bit.
Definition: adc.h:94
uint32_t simmask
bit in the SIM register
Definition: periph_cpu.h:448
gpio_t pin_mosi
MOSI pin used.
Definition: periph_cpu.h:437
emit interrupt on falling flank
Definition: gpio.h:130
uart_mode_t mode
UART mode: data bits, parity, stop bits.
Definition: periph_cpu.h:501
I2C_Type * i2c
Pointer to hardware module registers.
Definition: periph_cpu.h:421
configure as input with pull-up resistor
Definition: gpio.h:116
pwm_mode_t
Definition: periph_cpu.h:141
8 data bits, odd parity, 1 stop bit
Definition: periph_cpu.h:275
UART device configuration.
Definition: periph_cpu.h:166
gpio_mode_t
Available pin modes.
Definition: gpio.h:113
configure as input without pull resistor
Definition: gpio.h:114
IRQn_Type irqn
IRQ number for this module.
Definition: periph_cpu.h:426
DAC line configuration data.
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
Definition: periph_cpu.h:499
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
Definition: periph_cpu.h:116
low speed mode: ~10 kbit/s
Definition: i2c.h:182
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
Definition: periph_cpu.h:103
configure as output in open-drain mode without pull resistor
Definition: gpio.h:118
CPOL=1, CPHA=0.
Definition: spi.h:160
uart_type_t
UART hardware module types.
Definition: periph_cpu.h:476
port G
Definition: periph_cpu.h:42
SPI configuration structure type.
Definition: periph_cpu.h:271
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
Definition: periph_cpu.h:356
normal mode: ~100 kbit/s
Definition: i2c.h:183
configure as input with pull-down resistor
Definition: gpio.h:115
right aligned PWM
Definition: periph_cpu.h:143
8 data bits, even parity, 1 stop bit
Definition: periph_cpu.h:268
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:120
uint8_t scgc_bit
Clock enable bit, within the register.
Definition: periph_cpu.h:500
ADC_Type * dev
ADC module.
Definition: periph_cpu.h:307
gpio_t pin
pin to use
Definition: periph_cpu.h:313
Kinetis UART module type.
Definition: periph_cpu.h:477
port B
Definition: periph_cpu.h:37
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.
Definition: periph_cpu.h:487
fast plus mode: ~1000 kbit/s
Definition: i2c.h:185