periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * Copyright (C) 2017-2018 Eistec AB
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdbool.h>
26 
27 #include "cpu.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 #ifdef PORT_PCR_MUX
34 # define KINETIS_HAVE_PCR
35 #endif
36 
37 #ifdef SIM_PINSEL_REG
38 # define KINETIS_HAVE_PINSEL
39 #endif
40 
41 #ifdef ADC_CFG1_MODE_MASK
42 # define KINETIS_HAVE_ADC_K
43 #endif
44 
45 #ifdef SPI_CTAR_CPHA_MASK
46 # define KINETIS_HAVE_MK_SPI
47 #endif
48 
49 #ifdef LPTMR_CSR_TEN_MASK
50 # define KINETIS_HAVE_LPTMR
51 #endif
52 
57 #define HAVE_GPIO_T
58 typedef uint16_t gpio_t;
64 #define GPIO_UNDEF (0xffff)
65 
69 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
70 
71 #ifdef SIM_UIDH_UID_MASK
72 /* Kinetis Cortex-M4 has a 128 bit SIM UID */
76 #define CPUID_ADDR (&SIM->UIDH)
77 
81 #define CPUID_LEN (16U)
82 #else /* defined(SIM_UIDH_UID_MASK) */
83 /* Kinetis Cortex-M0+ has a 96 bit SIM UID */
87 #define CPUID_ADDR (&SIM->UIDMH)
88 
91 #define CPUID_LEN (12U)
92 #endif /* defined(SIM_UIDH_UID_MASK) */
93 
103 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
104 
111 #define SPI_HWCS(x) (x)
112 
116 #define SPI_HWCS_NUMOF (5)
117 
122 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
123 #define PERIPH_SPI_NEEDS_TRANSFER_REG 1
124 #define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
125 
130 #define PERIPH_TIMER_PROVIDES_SET
131 
136 #define PM_NUM_MODES (3U)
137 enum {
138  KINETIS_PM_LLS = 0,
139  KINETIS_PM_VLPS = 1,
140  KINETIS_PM_STOP = 2,
141  KINETIS_PM_WAIT = 3,
142 };
143 #if MODULE_PM_LAYERED
144 #include "pm_layered.h"
148 #define PM_BLOCK(x) pm_block(x)
149 
152 #define PM_UNBLOCK(x) pm_unblock(x)
153 #else
154 /* ignore these calls when not using pm_layered */
155 #define PM_BLOCK(x)
156 #define PM_UNBLOCK(x)
157 #endif
158 
160 #ifdef RTC
161 /* All Kinetis CPUs have exactly one RTC hardware module, except for the KL02
162  * family which don't have an RTC at all */
167 #define RTT_FREQUENCY (1)
168 #define RTT_MAX_VALUE (0xffffffff)
169 
170 #endif
171 
172 #ifndef DOXYGEN
173 
177 #define HAVE_GPIO_MODE_T
178 typedef enum {
179  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
180  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
181  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
182  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
183  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
184  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
185 } gpio_mode_t;
187 #endif /* ndef DOXYGEN */
188 
189 #ifdef KINETIS_HAVE_PCR
190 
195 typedef enum {
196  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
197  GPIO_AF_GPIO = PORT_PCR_MUX(1),
198  GPIO_AF_2 = PORT_PCR_MUX(2),
199  GPIO_AF_3 = PORT_PCR_MUX(3),
200  GPIO_AF_4 = PORT_PCR_MUX(4),
201  GPIO_AF_5 = PORT_PCR_MUX(5),
202  GPIO_AF_6 = PORT_PCR_MUX(6),
203  GPIO_AF_7 = PORT_PCR_MUX(7),
204 #ifdef PORT_PCR_ODE_MASK
205  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
206 #endif
207  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
208  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
209 } gpio_pcr_t;
210 #endif /* KINETIS_HAVE_PCR */
211 
212 #ifndef DOXYGEN
213 
217 #ifdef KINETIS_HAVE_PCR
218 #define HAVE_GPIO_FLANK_T
219 typedef enum {
220  GPIO_RISING = PORT_PCR_IRQC(0x9),
221  GPIO_FALLING = PORT_PCR_IRQC(0xa),
222  GPIO_BOTH = PORT_PCR_IRQC(0xb),
223 } gpio_flank_t;
224 #endif /* KINETIS_HAVE_PCR */
225 
226 #endif /* ndef DOXYGEN */
227 
233 enum {
234  PORT_A = 0,
235  PORT_B = 1,
236  PORT_C = 2,
237  PORT_D = 3,
238  PORT_E = 4,
239  PORT_F = 5,
240  PORT_G = 6,
242 };
243 
244 #ifndef DOXYGEN
245 
249 #define HAVE_ADC_RES_T
250 #ifdef KINETIS_HAVE_ADC_K
251 typedef enum {
252  ADC_RES_6BIT = (0xfe),
253  ADC_RES_8BIT = ADC_CFG1_MODE(0),
254  ADC_RES_10BIT = ADC_CFG1_MODE(2),
255  ADC_RES_12BIT = ADC_CFG1_MODE(1),
256  ADC_RES_14BIT = (0xff),
257  ADC_RES_16BIT = ADC_CFG1_MODE(3)
258 } adc_res_t;
259 #endif /* KINETIS_HAVE_ADC_K */
260 
262 #if defined(FTM_CnSC_MSB_MASK)
263 
266 #define PWM_CHAN_MAX (4U)
267 
272 #define HAVE_PWM_MODE_T
273 typedef enum {
274  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
275  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
276  PWM_CENTER = (FTM_CnSC_MSB_MASK)
277 } pwm_mode_t;
278 #endif /* defined(FTM_CnSC_MSB_MASK) */
279 #endif /* ndef DOXYGEN */
280 
284 typedef enum {
288 #if defined(UART_C1_M_MASK) || DOXYGEN
289  /* LPUART and UART mode bits coincide, so the same setting for UART works on
290  * the LPUART as well */
291  UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
292 #elif defined(LPUART_CTRL_M_MASK)
293  /* For CPUs which only have the LPUART */
294  UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
295 #endif
297 #if defined(UART_C1_M_MASK) || DOXYGEN
298  UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
299 #elif defined(LPUART_CTRL_M_MASK)
300  /* For CPUs which only have the LPUART */
301  UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
302 #endif
303 } uart_mode_t;
304 
305 #ifndef DOXYGEN
306 
311 #ifdef KINETIS_HAVE_MK_SPI
312 #define HAVE_SPI_MODE_T
313 typedef enum {
314  SPI_MODE_0 = 0,
315  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
316  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
317  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
318 } spi_mode_t;
320 #endif /* KINETIS_HAVE_MK_SPI */
321 #endif /* ndef DOXYGEN */
322 
326 typedef struct {
330  ADC_Type *dev;
336  gpio_t pin;
343  uint8_t chan;
349  uint8_t avg;
350 } adc_conf_t;
351 
355 #define ADC_AVG_NONE (0)
356 
359 #define ADC_AVG_MAX (ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3))
360 
361 #if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
362 
365 typedef struct {
366  DAC_Type *dev;
367  volatile uint32_t *scgc_addr;
368  uint8_t scgc_bit;
369 } dac_conf_t;
370 #endif
371 
375 typedef struct {
377  uint8_t prescaler_ch;
379  uint8_t count_ch;
380 } pit_conf_t;
381 
382 #ifdef KINETIS_HAVE_LPTMR
383 
386 typedef struct {
388  LPTMR_Type *dev;
390  uint32_t base_freq;
392  uint8_t src;
394  uint8_t irqn;
395 } lptmr_conf_t;
396 #endif /* KINETIS_HAVE_LPTMR */
397 
398 #ifdef FTM_CnSC_MSB_MASK
399 
402 typedef struct {
403  FTM_Type* ftm;
404  struct {
405  gpio_t pin;
406  uint8_t af;
407  uint8_t ftm_chan;
408  } chan[PWM_CHAN_MAX];
409  uint8_t chan_numof;
410  uint8_t ftm_num;
411 #ifdef KINETIS_HAVE_PINSEL
412  volatile uint32_t *pinsel;
413  uint32_t pinsel_mask;
414  uint32_t pinsel_val;
415 #endif
416 } pwm_conf_t;
417 #endif
418 
419 #ifndef DOXYGEN
420 #define HAVE_I2C_SPEED_T
421 typedef enum {
422  I2C_SPEED_LOW = 10000ul,
423  I2C_SPEED_NORMAL = 100000ul,
424  I2C_SPEED_FAST = 400000ul,
425  I2C_SPEED_FAST_PLUS = 1000000ul,
426  /* High speed is not supported without external hardware hacks */
427  I2C_SPEED_HIGH = 3400000ul,
428 } i2c_speed_t;
433 #define PERIPH_I2C_NEED_READ_REG
434 #define PERIPH_I2C_NEED_READ_REGS
435 #define PERIPH_I2C_NEED_WRITE_REG
436 #define PERIPH_I2C_NEED_WRITE_REGS
437 
438 #endif /* !defined(DOXYGEN) */
439 
443 typedef struct {
444  I2C_Type *i2c;
445  gpio_t scl_pin;
446  gpio_t sda_pin;
447  uint32_t freq;
448  i2c_speed_t speed;
450  uint32_t scl_pcr;
451  uint32_t sda_pcr;
452 } i2c_conf_t;
453 
457 typedef struct {
458  SPI_Type *dev;
459  gpio_t pin_miso;
460  gpio_t pin_mosi;
461  gpio_t pin_clk;
462  gpio_t pin_cs[SPI_HWCS_NUMOF];
463 #ifdef KINETIS_HAVE_PCR
464  gpio_pcr_t pcr;
465 #endif /* KINETIS_HAVE_PCR */
466 #ifdef KINETIS_HAVE_PINSEL
467  volatile uint32_t *pinsel;
468  uint32_t pinsel_mask;
469  uint32_t pinsel_val;
470 #endif
471  uint32_t simmask;
472 } spi_conf_t;
473 
477 enum {
479 #ifdef KINETIS_HAVE_LPTMR
480  TIMER_LPTMR,
481 #endif /* KINETIS_HAVE_LPTMR */
482 };
483 
489 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
490 #ifdef KINETIS_HAVE_LPTMR
491 
492 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
493 #endif /* KINETIS_HAVE_LPTMR */
494 
499 typedef enum {
502 } uart_type_t;
503 
507 typedef struct {
508  void *dev;
509  uint32_t freq;
510  gpio_t pin_rx;
511  gpio_t pin_tx;
512 #ifdef KINETIS_HAVE_PCR
513  uint32_t pcr_rx;
514  uint32_t pcr_tx;
515 #endif
516 #ifdef KINETIS_HAVE_PINSEL
517  volatile uint32_t *pinsel;
518  uint32_t pinsel_mask;
519  uint32_t pinsel_val;
520 #endif
522  volatile uint32_t *scgc_addr;
523  uint8_t scgc_bit;
525  uart_type_t type;
526 } uart_conf_t;
527 
528 #if !defined(KINETIS_HAVE_PLL)
529 #if defined(MCG_C6_PLLS_MASK) || DOXYGEN
530 
533 #define KINETIS_HAVE_PLL 1
534 #else
535 #define KINETIS_HAVE_PLL 0
536 #endif
537 #endif /* !defined(KINETIS_HAVE_PLL) */
538 
539 #ifdef MODULE_PERIPH_MCG
540 
543 typedef enum kinetis_mcg_mode {
544  KINETIS_MCG_MODE_FEI = 0,
545  KINETIS_MCG_MODE_FEE = 1,
546  KINETIS_MCG_MODE_FBI = 2,
547  KINETIS_MCG_MODE_FBE = 3,
548  KINETIS_MCG_MODE_BLPI = 4,
549  KINETIS_MCG_MODE_BLPE = 5,
550 #if KINETIS_HAVE_PLL
551  KINETIS_MCG_MODE_PBE = 6,
552  KINETIS_MCG_MODE_PEE = 7,
553 #endif
554  KINETIS_MCG_MODE_NUMOF,
555 } kinetis_mcg_mode_t;
556 
560 typedef enum {
562  KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
564  KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
566  KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
568  KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
570  KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
572  KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
574  KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
576  KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
577 } kinetis_mcg_fll_t;
578 
582 typedef enum {
583  KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
584  KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
585  KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
586 } kinetis_mcg_erc_range_t;
587 
594 typedef enum {
603  KINETIS_CLOCK_OSC0_EN = (1 << 0),
612  KINETIS_CLOCK_RTCOSC_EN = (1 << 1),
627  KINETIS_CLOCK_USE_FAST_IRC = (1 << 2),
636  KINETIS_CLOCK_MCGIRCLK_EN = (1 << 3),
647  KINETIS_CLOCK_MCGIRCLK_STOP_EN = (1 << 4),
648 } kinetis_clock_flags_t;
649 
653 typedef struct {
663  uint32_t clkdiv1;
675  uint32_t rtc_clc;
689  uint32_t osc32ksel;
695  unsigned int clock_flags;
701  kinetis_mcg_mode_t default_mode;
707  kinetis_mcg_erc_range_t erc_range;
718  uint8_t osc_clc;
728  uint8_t oscsel;
738  uint8_t fcrdiv;
748  uint8_t fll_frdiv;
755  kinetis_mcg_fll_t fll_factor_fei;
762  kinetis_mcg_fll_t fll_factor_fee;
763 #if KINETIS_HAVE_PLL
764 
773  uint8_t pll_prdiv;
783  uint8_t pll_vdiv;
784 #endif /* KINETIS_HAVE_PLL */
785 } clock_config_t;
786 #endif /* MODULE_PERIPH_MCG */
787 
793 void gpio_init_port(gpio_t pin, uint32_t pcr);
794 
795 #ifdef __cplusplus
796 }
797 #endif
798 
799 #endif /* PERIPH_CPU_H */
800 
port C
Definition: periph_cpu.h:38
fast mode: ~400 kbit/s
Definition: i2c.h:178
CPOL=0, CPHA=1.
Definition: spi.h:159
configure as output in push-pull mode
Definition: gpio.h:122
high speed mode: ~3400 kbit/s
Definition: i2c.h:180
Layered low power mode infrastructure.
I2C configuration options.
Definition: periph_cpu.h:128
not supported
Definition: periph_cpu.h:162
emit interrupt on rising flank
Definition: periph_cpu.h:82
IRQn_Type irqn
IRQ number for this module.
Definition: periph_cpu.h:521
ADC resolution: 12 bit.
Definition: adc.h:97
gpio_t pin_tx
TX pin.
Definition: periph_cpu.h:511
uint8_t avg
Hardware averaging configuration.
Definition: periph_cpu.h:349
CPU specific timer PIT module configuration.
Definition: periph_cpu.h:375
PIT.
Definition: periph_cpu.h:478
Kinetis Low-power UART (LPUART) module type.
Definition: periph_cpu.h:501
#define PWM_CHAN_MAX
PWM configuration structure.
Definition: periph_conf.h:229
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:93
uint8_t prescaler_ch
Prescaler channel.
Definition: periph_cpu.h:377
gpio_t pin_miso
MISO pin used.
Definition: periph_cpu.h:459
enum IRQn IRQn_Type
Interrupt Number Definition.
CPOL=0, CPHA=0.
Definition: spi.h:158
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:458
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:175
gpio_flank_t
Definition: periph_cpu.h:80
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
Definition: periph_cpu.h:509
uint8_t chan
ADC channel.
Definition: periph_cpu.h:343
PWM device configuration.
uart_type_t type
Hardware module type (KINETIS_UART or KINETIS_LPUART)
Definition: periph_cpu.h:525
emit interrupt on both flanks
Definition: periph_cpu.h:83
uart_mode_t
UART transmission modes.
Definition: periph_cpu.h:284
port F
Definition: periph_cpu.h:41
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
8 data bits, no parity, 1 stop bit
Definition: periph_cpu.h:286
ADC resolution: 14 bit.
Definition: adc.h:98
left aligned PWM
Definition: periph_cpu.h:160
ADC resolution: 10 bit.
Definition: adc.h:96
CPOL=1, CPHA=1.
Definition: spi.h:161
uint32_t sda_pcr
PORT module PCR setting for the SDA pin.
Definition: periph_cpu.h:451
port E
Definition: periph_cpu.h:40
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
gpio_t adc_conf_t
ADC configuration wrapper.
Definition: periph_cpu.h:315
gpio_t pin_clk
CLK pin used.
Definition: periph_cpu.h:461
port D
Definition: periph_cpu.h:39
uint32_t freq
I2C module clock frequency, usually CLOCK_BUSCLOCK or CLOCK_CORECLOCK.
Definition: periph_cpu.h:447
ADC resolution: 16 bit.
Definition: adc.h:99
port A
Definition: periph_cpu.h:36
ADC resolution: 8 bit.
Definition: adc.h:95
uint32_t scl_pcr
PORT module PCR setting for the SCL pin.
Definition: periph_cpu.h:450
ADC resolution: 6 bit.
Definition: adc.h:94
uint32_t simmask
bit in the SIM register
Definition: periph_cpu.h:471
gpio_t pin_mosi
MOSI pin used.
Definition: periph_cpu.h:460
emit interrupt on falling flank
Definition: periph_cpu.h:81
uart_mode_t mode
UART mode: data bits, parity, stop bits.
Definition: periph_cpu.h:524
I2C_Type * i2c
Pointer to hardware module registers.
Definition: periph_cpu.h:444
configure as input with pull-up resistor
Definition: gpio.h:121
pwm_mode_t
Definition: periph_cpu.h:159
8 data bits, odd parity, 1 stop bit
Definition: periph_cpu.h:298
UART device configuration.
Definition: periph_cpu.h:166
configure as input without pull resistor
Definition: gpio.h:119
IRQn_Type irqn
IRQ number for this module.
Definition: periph_cpu.h:449
DAC line configuration data.
Definition: periph_cpu.h:502
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
Definition: periph_cpu.h:522
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
Definition: periph_cpu.h:116
low speed mode: ~10 kbit/s
Definition: i2c.h:176
overall number of available ports
Definition: periph_cpu.h:241
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
Definition: periph_cpu.h:103
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
CPOL=1, CPHA=0.
Definition: spi.h:160
uart_type_t
UART hardware module types.
Definition: periph_cpu.h:499
port G
Definition: periph_cpu.h:42
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:70
SPI configuration structure type.
Definition: periph_cpu.h:273
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
Definition: periph_cpu.h:379
normal mode: ~100 kbit/s
Definition: i2c.h:177
configure as input with pull-down resistor
Definition: gpio.h:120
right aligned PWM
Definition: periph_cpu.h:161
8 data bits, even parity, 1 stop bit
Definition: periph_cpu.h:291
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
uint8_t scgc_bit
Clock enable bit, within the register.
Definition: periph_cpu.h:523
ADC_Type * dev
ADC module.
Definition: periph_cpu.h:330
gpio_t pin
pin to use
Definition: periph_cpu.h:336
Kinetis UART module type.
Definition: periph_cpu.h:500
port B
Definition: periph_cpu.h:37
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.
Definition: periph_cpu.h:510
fast plus mode: ~1000 kbit/s
Definition: i2c.h:179