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periph_cpu.h
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1/*
2 * Copyright (C) 2015-2016 Freie Universität Berlin
3 * Copyright (C) 2017-2018 Eistec AB
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CPU_H
22#define PERIPH_CPU_H
23
24#include <stdint.h>
25#include <stdbool.h>
26
27#include "cpu.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33#ifdef PORT_PCR_MUX
34# define KINETIS_HAVE_PCR
35#endif
36
37#ifdef SIM_PINSEL_REG
38# define KINETIS_HAVE_PINSEL
39#endif
40
41#ifdef ADC_CFG1_MODE_MASK
42# define KINETIS_HAVE_ADC_K
43#endif
44
45#ifdef SPI_CTAR_CPHA_MASK
46# define KINETIS_HAVE_MK_SPI
47#endif
48
49#ifdef LPTMR_CSR_TEN_MASK
50# define KINETIS_HAVE_LPTMR
51#endif
52
57#define HAVE_GPIO_T
58typedef uint16_t gpio_t;
64#define GPIO_UNDEF (0xffff)
65
69#define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
70
71#ifdef SIM_UIDH_UID_MASK
72/* Kinetis Cortex-M4 has a 128 bit SIM UID */
76#define CPUID_ADDR (&SIM->UIDH)
77
81#define CPUID_LEN (16U)
82#else /* defined(SIM_UIDH_UID_MASK) */
83/* Kinetis Cortex-M0+ has a 96 bit SIM UID */
87#define CPUID_ADDR (&SIM->UIDMH)
91#define CPUID_LEN (12U)
92#endif /* defined(SIM_UIDH_UID_MASK) */
93
103#define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
104
111#define SPI_HWCS(x) (x)
112
116#define SPI_HWCS_NUMOF (5)
117
121#define SPI_CS_UNDEF (GPIO_UNDEF)
122
123#ifndef DOXYGEN
128#define HAVE_SPI_CS_T
129typedef uint32_t spi_cs_t;
131#endif
132
137#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
138#define PERIPH_SPI_NEEDS_TRANSFER_REG 1
139#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
145#define PERIPH_TIMER_PROVIDES_SET
146
150#define TIMER_CHANNEL_NUMOF 1
151
156#define PM_NUM_MODES (4U)
157enum {
158 KINETIS_PM_LLS = 0,
159 KINETIS_PM_VLPS = 1,
160 KINETIS_PM_STOP = 2,
161 KINETIS_PM_WAIT = 3,
162};
163#if MODULE_PM_LAYERED
164#include "pm_layered.h"
168#define PM_BLOCK(x) pm_block(x)
172#define PM_UNBLOCK(x) pm_unblock(x)
173#else
174/* ignore these calls when not using pm_layered */
175#define PM_BLOCK(x)
176#define PM_UNBLOCK(x)
177#endif
180#ifndef DOXYGEN
185#define HAVE_GPIO_MODE_T
186typedef enum {
187 GPIO_IN = GPIO_MODE(0, 0, 0, 0),
188 GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
189 GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
190 GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
191 GPIO_OD = GPIO_MODE(1, 0, 1, 1),
192 GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
195#endif /* ndef DOXYGEN */
196
197#ifdef KINETIS_HAVE_PCR
203typedef enum {
204 GPIO_AF_ANALOG = PORT_PCR_MUX(0),
205 GPIO_AF_GPIO = PORT_PCR_MUX(1),
206 GPIO_AF_2 = PORT_PCR_MUX(2),
207 GPIO_AF_3 = PORT_PCR_MUX(3),
208 GPIO_AF_4 = PORT_PCR_MUX(4),
209 GPIO_AF_5 = PORT_PCR_MUX(5),
210 GPIO_AF_6 = PORT_PCR_MUX(6),
211 GPIO_AF_7 = PORT_PCR_MUX(7),
212#ifdef PORT_PCR_ODE_MASK
213 GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
214#endif
215 GPIO_PCR_PD = (PORT_PCR_PE_MASK),
216 GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
217} gpio_pcr_t;
218#endif /* KINETIS_HAVE_PCR */
219
220#ifndef DOXYGEN
225#ifdef KINETIS_HAVE_PCR
226#define HAVE_GPIO_FLANK_T
227typedef enum {
228 GPIO_RISING = PORT_PCR_IRQC(0x9),
229 GPIO_FALLING = PORT_PCR_IRQC(0xa),
230 GPIO_BOTH = PORT_PCR_IRQC(0xb),
232#endif /* KINETIS_HAVE_PCR */
234#endif /* ndef DOXYGEN */
235
241enum {
242 PORT_A = 0,
243 PORT_B = 1,
244 PORT_C = 2,
245 PORT_D = 3,
246 PORT_E = 4,
247 PORT_F = 5,
248 PORT_G = 6,
251
252#ifndef DOXYGEN
257#define HAVE_ADC_RES_T
258#ifdef KINETIS_HAVE_ADC_K
259typedef enum {
260 ADC_RES_6BIT = (0xfe),
261 ADC_RES_8BIT = ADC_CFG1_MODE(0),
262 ADC_RES_10BIT = ADC_CFG1_MODE(2),
263 ADC_RES_12BIT = ADC_CFG1_MODE(1),
264 ADC_RES_14BIT = (0xff),
265 ADC_RES_16BIT = ADC_CFG1_MODE(3)
266} adc_res_t;
267#endif /* KINETIS_HAVE_ADC_K */
270#if defined(FTM_CnSC_MSB_MASK)
274#define PWM_CHAN_MAX (4U)
275
280#define HAVE_PWM_MODE_T
281typedef enum {
282 PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
283 PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
284 PWM_CENTER = (FTM_CnSC_MSB_MASK)
285} pwm_mode_t;
286#endif /* defined(FTM_CnSC_MSB_MASK) */
287#endif /* ndef DOXYGEN */
288
292typedef enum {
296#if defined(UART_C1_M_MASK) || DOXYGEN
297 /* LPUART and UART mode bits coincide, so the same setting for UART works on
298 * the LPUART as well */
299 UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
300#elif defined(LPUART_CTRL_M_MASK)
301 /* For CPUs which only have the LPUART */
302 UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
303#endif
305#if defined(UART_C1_M_MASK) || DOXYGEN
306 UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
307#elif defined(LPUART_CTRL_M_MASK)
308 /* For CPUs which only have the LPUART */
309 UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
310#endif
312
313#ifndef DOXYGEN
319#ifdef KINETIS_HAVE_MK_SPI
320#define HAVE_SPI_MODE_T
321typedef enum {
322#if defined(SPI_CTAR_CPHA_MASK)
323 SPI_MODE_0 = 0,
324 SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
325 SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
326 SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
327#elif defined(SPI_C1_CPHA_MASK)
328 SPI_MODE_0 = 0,
329 SPI_MODE_1 = (SPI_C1_CPHA_MASK),
330 SPI_MODE_2 = (SPI_C1_CPOL_MASK),
331 SPI_MODE_3 = (SPI_C1_CPOL_MASK | SPI_C1_CPHA_MASK)
332#endif
333} spi_mode_t;
335#endif /* KINETIS_HAVE_MK_SPI */
336#endif /* ndef DOXYGEN */
337
341typedef struct {
345 ADC_Type *dev;
351 gpio_t pin;
358 uint8_t chan;
364 uint8_t avg;
365} adc_conf_t;
366
370#define ADC_AVG_NONE (0)
374#define ADC_AVG_MAX (ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3))
375
376#if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
380typedef struct {
381 DAC_Type *dev;
382 volatile uint32_t *scgc_addr;
383 uint8_t scgc_bit;
384} dac_conf_t;
385#endif
386
390typedef struct {
394 uint8_t count_ch;
395} pit_conf_t;
396
397#ifdef KINETIS_HAVE_LPTMR
401typedef struct {
403 LPTMR_Type *dev;
405 uint32_t base_freq;
407 uint8_t src;
409 uint8_t irqn;
410} lptmr_conf_t;
411#endif /* KINETIS_HAVE_LPTMR */
412
413#ifdef FTM_CnSC_MSB_MASK
417typedef struct {
418 FTM_Type* ftm;
419 struct {
420 gpio_t pin;
421 uint8_t af;
422 uint8_t ftm_chan;
423 } chan[PWM_CHAN_MAX];
424 uint8_t chan_numof;
425 uint8_t ftm_num;
426#ifdef KINETIS_HAVE_PINSEL
427 volatile uint32_t *pinsel;
428 uint32_t pinsel_mask;
429 uint32_t pinsel_val;
430#endif
431} pwm_conf_t;
432#endif
433
434#ifndef DOXYGEN
435#define HAVE_I2C_SPEED_T
436typedef enum {
437 I2C_SPEED_LOW = 10000ul,
438 I2C_SPEED_NORMAL = 100000ul,
439 I2C_SPEED_FAST = 400000ul,
440 I2C_SPEED_FAST_PLUS = 1000000ul,
441 /* High speed is not supported without external hardware hacks */
442 I2C_SPEED_HIGH = 3400000ul,
448#define PERIPH_I2C_NEED_READ_REG
449#define PERIPH_I2C_NEED_READ_REGS
450#define PERIPH_I2C_NEED_WRITE_REG
451#define PERIPH_I2C_NEED_WRITE_REGS
453#endif /* !defined(DOXYGEN) */
454
458typedef struct {
459 I2C_Type *i2c;
460 gpio_t scl_pin;
461 gpio_t sda_pin;
462 uint32_t freq;
463 i2c_speed_t speed;
464 IRQn_Type irqn;
465 uint32_t scl_pcr;
466 uint32_t sda_pcr;
467} i2c_conf_t;
468
472typedef struct {
473 SPI_Type *dev;
474 gpio_t pin_miso;
475 gpio_t pin_mosi;
476 gpio_t pin_clk;
478#ifdef KINETIS_HAVE_PCR
479 gpio_pcr_t pcr;
480#endif /* KINETIS_HAVE_PCR */
481#ifdef KINETIS_HAVE_PINSEL
482 volatile uint32_t *pinsel;
483 uint32_t pinsel_mask;
484 uint32_t pinsel_val;
485#endif
486 uint32_t simmask;
487} spi_conf_t;
488
492enum {
494#ifdef KINETIS_HAVE_LPTMR
495 TIMER_LPTMR,
496#endif /* KINETIS_HAVE_LPTMR */
497};
498
504#define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
505#ifdef KINETIS_HAVE_LPTMR
507#define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
508#endif /* KINETIS_HAVE_LPTMR */
515#define RTT_DEV (TIMER_LPTMR_DEV(0))
516#define RTT_MAX_VALUE (0x0000ffff)
517#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
518#define RTT_MAX_FREQUENCY (32768U) /* in Hz */
519#define RTT_MIN_FREQUENCY (1U) /* in Hz */
520#ifndef RTT_FREQUENCY
521#define RTT_FREQUENCY RTT_MAX_FREQUENCY
522#endif
523#if IS_USED(MODULE_PERIPH_RTT)
524/* On kinetis periph_rtt is built on top on an LPTIMER so if used it
525 will conflict with xtimer, if a LPTIMER backend and RTT are needed
526 consider using ztimer */
527#define KINETIS_XTIMER_SOURCE_PIT 1
528#endif
529/* When setting a new compare value, the value must be at least 5 more
530 than the current sleep timer value. Otherwise, the timer compare
531 event may be lost. */
541
545typedef struct {
546 void *dev;
547 uint32_t freq;
548 gpio_t pin_rx;
549 gpio_t pin_tx;
550#ifdef KINETIS_HAVE_PCR
551 uint32_t pcr_rx;
552 uint32_t pcr_tx;
553#endif
554#ifdef KINETIS_HAVE_PINSEL
555 volatile uint32_t *pinsel;
556 uint32_t pinsel_mask;
557 uint32_t pinsel_val;
558#endif
560 volatile uint32_t *scgc_addr;
561 uint8_t scgc_bit;
565
566#if !defined(KINETIS_HAVE_PLL) && defined(MODULE_PERIPH_MCG) \
567 && defined(MCG_C6_PLLS_MASK) || DOXYGEN
571#define KINETIS_HAVE_PLL 1
572#else
573#define KINETIS_HAVE_PLL 0
574#endif
575
576#ifdef MODULE_PERIPH_MCG_LITE
580typedef enum kinetis_mcg_mode {
581 KINETIS_MCG_MODE_LIRC8M = 0,
582 KINETIS_MCG_MODE_HIRC = 1,
583 KINETIS_MCG_MODE_EXT = 2,
584 KINETIS_MCG_MODE_LIRC2M = 3,
585 KINETIS_MCG_MODE_NUMOF,
586} kinetis_mcg_mode_t;
587#endif /* MODULE_PERIPH_MCG_LITE */
588
589#ifdef MODULE_PERIPH_MCG
593typedef enum kinetis_mcg_mode {
594 KINETIS_MCG_MODE_FEI = 0,
595 KINETIS_MCG_MODE_FEE = 1,
596 KINETIS_MCG_MODE_FBI = 2,
597 KINETIS_MCG_MODE_FBE = 3,
598 KINETIS_MCG_MODE_BLPI = 4,
599 KINETIS_MCG_MODE_BLPE = 5,
600#if KINETIS_HAVE_PLL
601 KINETIS_MCG_MODE_PBE = 6,
602 KINETIS_MCG_MODE_PEE = 7,
603#endif
604 KINETIS_MCG_MODE_NUMOF,
605} kinetis_mcg_mode_t;
606
610typedef enum {
612 KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
614 KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
616 KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
618 KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
620 KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
622 KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
624 KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
626 KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
627} kinetis_mcg_fll_t;
628
629#endif /* MODULE_PERIPH_MCG */
630#if defined(MODULE_PERIPH_MCG) || defined(MODULE_PERIPH_MCG_LITE)
631
635typedef enum {
636 KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
637 KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
638 KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
639} kinetis_mcg_erc_range_t;
640
647typedef enum {
656 KINETIS_CLOCK_OSC0_EN = (1 << 0),
665 KINETIS_CLOCK_RTCOSC_EN = (1 << 1),
682 KINETIS_CLOCK_USE_FAST_IRC = (1 << 2),
691 KINETIS_CLOCK_MCGIRCLK_EN = (1 << 3),
702 KINETIS_CLOCK_MCGIRCLK_STOP_EN = (1 << 4),
713 KINETIS_CLOCK_MCGPCLK_EN = (1 << 5),
714} kinetis_clock_flags_t;
715
719typedef struct {
729 uint32_t clkdiv1;
741 uint32_t rtc_clc;
755 uint32_t osc32ksel;
761 unsigned int clock_flags;
767 kinetis_mcg_mode_t default_mode;
773 kinetis_mcg_erc_range_t erc_range;
784 uint8_t osc_clc;
785#ifdef MODULE_PERIPH_MCG
795 uint8_t oscsel;
796#endif /* MODULE_PERIPH_MCG */
808 uint8_t fcrdiv;
809#ifdef MODULE_PERIPH_MCG_LITE
821 uint8_t lirc_div2;
822#else
832 uint8_t fll_frdiv;
839 kinetis_mcg_fll_t fll_factor_fei;
846 kinetis_mcg_fll_t fll_factor_fee;
847#if KINETIS_HAVE_PLL
857 uint8_t pll_prdiv;
867 uint8_t pll_vdiv;
868#endif /* KINETIS_HAVE_PLL */
869#endif /* MODULE_PERIPH_MCG */
870} clock_config_t;
871#endif /* MODULE_PERIPH_MCG || MODULE_PERIPH_MCG_LITE */
878void gpio_init_port(gpio_t pin, uint32_t pcr);
879
880#ifdef __cplusplus
881}
882#endif
883
884#endif /* PERIPH_CPU_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_G
port G
Definition periph_cpu.h:53
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_F
port F
Definition periph_cpu.h:52
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
gpio_flank_t
Definition periph_cpu.h:180
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:165
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:164
i2c_speed_t
Definition periph_cpu.h:276
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition periph_cpu.h:280
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition periph_cpu.h:277
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition periph_cpu.h:282
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:279
pwm_mode_t
@ PWM_CENTER
center aligned
@ PWM_LEFT
left aligned
@ PWM_RIGHT
right aligned
#define PWM_CHAN_MAX
PWM configuration structure.
gpio_t adc_conf_t
ADC configuration wrapper.
Definition periph_cpu.h:337
uart_type_t
UART hardware module types.
Definition cpu_uart.h:37
#define GPIO_MODE(x, y)
Internal macro for combining pin mode (x) and pull-up/down (y).
Definition periph_cpu.h:152
enum IRQn IRQn_Type
Interrupt Number Definition.
adc_res_t
Possible ADC resolution settings.
Definition adc.h:93
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition adc.h:99
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:95
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:98
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:94
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:96
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:97
gpio_t spi_cs_t
Chip select pin type overlaps with gpio_t so it can be casted to this.
Definition spi.h:135
@ TIMER_PIT
PIT.
Definition periph_cpu.h:493
uart_type_t
UART hardware module types.
Definition periph_cpu.h:537
@ KINETIS_LPUART
Kinetis Low-power UART (LPUART) module type.
Definition periph_cpu.h:539
@ KINETIS_UART
Kinetis UART module type.
Definition periph_cpu.h:538
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
uart_mode_t
UART transmission modes.
Definition periph_cpu.h:292
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition periph_cpu.h:294
@ UART_MODE_8E1
8 data bits, even parity, 1 stop bit
Definition periph_cpu.h:299
@ UART_MODE_8O1
8 data bits, odd parity, 1 stop bit
Definition periph_cpu.h:306
@ GPIO_PORTS_NUMOF
overall number of available ports
Definition periph_cpu.h:249
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
Definition periph_cpu.h:116
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:82
Layered low power mode infrastructure.
uint8_t avg
Hardware averaging configuration.
Definition periph_cpu.h:364
ADC_Type * dev
ADC module.
Definition periph_cpu.h:345
DAC line configuration data.
Definition periph_cpu.h:301
I2C configuration structure.
Definition periph_cpu.h:299
uint32_t freq
I2C module clock frequency, usually CLOCK_BUSCLOCK or CLOCK_CORECLOCK.
Definition periph_cpu.h:462
I2C_Type * i2c
Pointer to hardware module registers.
Definition periph_cpu.h:459
uint32_t sda_pcr
PORT module PCR setting for the SDA pin.
Definition periph_cpu.h:466
uint32_t scl_pcr
PORT module PCR setting for the SCL pin.
Definition periph_cpu.h:465
CPU specific timer PIT module configuration.
Definition periph_cpu.h:390
uint8_t prescaler_ch
Prescaler channel.
Definition periph_cpu.h:392
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
Definition periph_cpu.h:394
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:337
gpio_t pin_clk
CLK pin used.
Definition periph_cpu.h:476
gpio_t pin_mosi
MOSI pin used.
Definition periph_cpu.h:475
gpio_t pin_miso
MISO pin used.
Definition periph_cpu.h:474
uint32_t simmask
bit in the SIM register
Definition periph_cpu.h:486
UART device configuration.
Definition periph_cpu.h:218
uart_type_t type
Hardware module type (KINETIS_UART or KINETIS_LPUART)
Definition periph_cpu.h:563
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.
Definition periph_cpu.h:548
gpio_t pin_tx
TX pin.
Definition periph_cpu.h:549
uint8_t scgc_bit
Clock enable bit, within the register.
Definition periph_cpu.h:561
uart_mode_t mode
UART mode: data bits, parity, stop bits.
Definition periph_cpu.h:562
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
Definition periph_cpu.h:560
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
Definition periph_cpu.h:547
IRQn_Type irqn
IRQ number for this module.
Definition periph_cpu.h:559