boards/pba-d-01-kw2x/include/periph_conf.h File Reference
#include "periph_cpu.h"
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Macros

Timer configuration
#define PIT_NUMOF   (2U)
 
#define PIT_CONFIG
 
#define LPTMR_NUMOF   (0U)
 
#define LPTMR_CONFIG   {}
 
#define TIMER_NUMOF   ((PIT_NUMOF) + (LPTMR_NUMOF))
 
#define PIT_BASECLOCK   (CLOCK_BUSCLOCK)
 
#define PIT_ISR_0   isr_pit1
 
#define PIT_ISR_1   isr_pit3
 
#define LPTMR_ISR_0   isr_lptmr0
 
I2C configuration
#define I2C_NUMOF   (1U)
 
#define I2C_0_EN   1
 
#define KINETIS_I2C_F_ICR_LOW   (0x3D)
 
#define KINETIS_I2C_F_MULT_LOW   (1)
 
#define KINETIS_I2C_F_ICR_NORMAL   (0x1F)
 
#define KINETIS_I2C_F_MULT_NORMAL   (1)
 
#define KINETIS_I2C_F_ICR_FAST   (0x17)
 
#define KINETIS_I2C_F_MULT_FAST   (0)
 
#define KINETIS_I2C_F_ICR_FAST_PLUS   (0x10)
 
#define KINETIS_I2C_F_MULT_FAST_PLUS   (0)
 
#define I2C_0_DEV   I2C1
 
#define I2C_0_CLKEN()   (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
 
#define I2C_0_CLKDIS()   (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
 
#define I2C_0_IRQ   I2C1_IRQn
 
#define I2C_0_IRQ_HANDLER   isr_i2c1
 
#define I2C_0_PORT   PORTE
 
#define I2C_0_PORT_CLKEN()   (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
 
#define I2C_0_PIN_AF   6
 
#define I2C_0_SDA_PIN   0
 
#define I2C_0_SCL_PIN   1
 
#define I2C_0_PORT_CFG   (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
 
RTT and RTC configuration
#define RTT_NUMOF   (1U)
 
#define RTC_NUMOF   (1U)
 
#define RTT_DEV   RTC
 
#define RTT_IRQ   RTC_IRQn
 
#define RTT_IRQ_PRIO   10
 
#define RTT_UNLOCK()   (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
 
#define RTT_ISR   isr_rtc
 
#define RTT_FREQUENCY   (1)
 
#define RTT_MAX_VALUE   (0xffffffff)
 

Clock system configuration

#define CLOCK_CORECLOCK   (48000000ul)
 
#define CLOCK_BUSCLOCK   (CLOCK_CORECLOCK / 1)
 
static const clock_config_t clock_config
 

UART configuration

#define UART_0_ISR   (isr_uart2_rx_tx)
 
#define UART_1_ISR   (isr_uart0_rx_tx)
 
#define UART_NUMOF   (sizeof(uart_config) / sizeof(uart_config[0]))
 
static const uart_conf_t uart_config []
 

ADC configuration

#define ADC_NUMOF   (sizeof(adc_config) / sizeof(adc_config[0]))
 
static const adc_conf_t adc_config []
 

PWM configuration

#define PWM_NUMOF   (sizeof(pwm_config) / sizeof(pwm_config[0]))
 
static const pwm_conf_t pwm_config []
 

SPI device configuration

Clock configuration values based on the configured 48Mhz module clock.

Auto-generated by: cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c

#define SPI_NUMOF   (sizeof(spi_config) / sizeof(spi_config[0]))
 
static const uint32_t spi_clk_config []
 
static const spi_conf_t spi_config []
 

Macro Definition Documentation

◆ PIT_CONFIG

#define PIT_CONFIG
Value:
{ \
{ \
.prescaler_ch = 0, \
.count_ch = 1, \
}, \
{ \
.prescaler_ch = 2, \
.count_ch = 3, \
}, \
}

Definition at line 70 of file boards/pba-d-01-kw2x/include/periph_conf.h.

Variable Documentation

◆ adc_config

const adc_conf_t adc_config[]
static
Initial value:
= {
{ .dev = ADC0, .pin = GPIO_PIN(PORT_E, 2), .chan = 1 },
{ .dev = ADC0, .pin = GPIO_PIN(PORT_E, 3), .chan = 1 },
{ .dev = ADC0, .pin = GPIO_PIN(PORT_D, 7), .chan = 22 },
{ .dev = ADC0, .pin = GPIO_PIN(PORT_D, 5), .chan = 6 },
{ .dev = ADC0, .pin = GPIO_PIN(PORT_E, 0), .chan = 10 },
{ .dev = ADC0, .pin = GPIO_PIN(PORT_E, 1), .chan = 11 }
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 134 of file boards/pba-d-01-kw2x/include/periph_conf.h.

◆ clock_config

const clock_config_t clock_config
static
Initial value:
= {
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
SIM_CLKDIV1_OUTDIV4(1),
.default_mode = KINETIS_MCG_MODE_PEE,
.fcrdiv = 0,
.oscsel = 0,
.clc = 0,
.fll_frdiv = 0b010,
.fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464,
.fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1280,
.pll_prdiv = 0b00001,
.pll_vdiv = 0b00000,
.enable_oscillator = false,
.select_fast_irc = true,
.enable_mcgirclk = false,
}
PLL Engaged External Mode.

Definition at line 36 of file boards/pba-d-01-kw2x/include/periph_conf.h.

◆ pwm_config

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.ftm = FTM0,
.chan = {
{ .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 1 },
{ .pin = GPIO_PIN(PORT_D, 4), .af = 4, .ftm_chan = 4 },
{ .pin = GPIO_PIN(PORT_D, 6), .af = 4, .ftm_chan = 6 },
{ .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 1 }
},
.chan_numof = 4,
.ftm_num = 0
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.

Definition at line 150 of file boards/pba-d-01-kw2x/include/periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = UART2,
.freq = CLOCK_BUSCLOCK,
.pin_rx = GPIO_PIN(PORT_D, 2),
.pin_tx = GPIO_PIN(PORT_D, 3),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART2_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART2_SHIFT,
.mode = UART_MODE_8N1,
.type = KINETIS_UART,
},
{
.dev = UART0,
.freq = CLOCK_CORECLOCK,
.pin_rx = GPIO_PIN(PORT_D, 6),
.pin_tx = GPIO_PIN(PORT_D, 7),
.pcr_rx = PORT_PCR_MUX(3),
.pcr_tx = PORT_PCR_MUX(3),
.irqn = UART0_RX_TX_IRQn,
.scgc_addr = &SIM->SCGC4,
.scgc_bit = SIM_SCGC4_UART0_SHIFT,
.mode = UART_MODE_8N1,
.type = KINETIS_UART,
}
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
cc2538_uart_t *const UART0
UART0 Instance.
8 data bits, no parity, 1 stop bit
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:144
#define CLOCK_CORECLOCK
Core clock frequency, used by the ARM core and certain hardware modules in Kinetis CPUs...
Definition: mcg.h:137
Kinetis UART module type.

Definition at line 95 of file boards/pba-d-01-kw2x/include/periph_conf.h.