periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2017 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CPU_H
21 #define PERIPH_CPU_H
22 
23 #include "mutex.h"
24 
25 #include "cpu_conf.h"
26 
27 #include "em_adc.h"
28 #include "em_cmu.h"
29 #include "em_device.h"
30 #include "em_gpio.h"
31 #include "em_timer.h"
32 #include "em_usart.h"
33 #ifdef _SILICON_LABS_32B_SERIES_0
34 #include "em_dac.h"
35 #endif
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
45 #define ADC_MODE(x, y) ((y << 4) | x)
46 
50 #define ADC_MODE_UNDEF(x) (ADC_MODE(x, 15))
51 
52 #ifndef DOXYGEN
53 
57 #define HAVE_ADC_RES_T
58 typedef enum {
59  ADC_RES_6BIT = ADC_MODE(adcRes6Bit, 0),
60  ADC_RES_8BIT = ADC_MODE(adcRes8Bit, 0),
61  ADC_RES_10BIT = ADC_MODE(adcRes12Bit, 2),
62  ADC_RES_12BIT = ADC_MODE(adcRes12Bit, 0),
65 } adc_res_t;
67 #endif /* ndef DOXYGEN */
68 
72 typedef struct {
73  ADC_TypeDef *dev;
74  CMU_Clock_TypeDef cmu;
75 } adc_conf_t;
76 
80 typedef struct {
81  uint8_t dev;
82 #ifdef _SILICON_LABS_32B_SERIES_0
83  ADC_SingleInput_TypeDef input;
84 #else
85  ADC_PosSel_TypeDef input;
86 #endif
87  ADC_Ref_TypeDef reference;
88  ADC_AcqTime_TypeDef acq_time;
90 
94 #define CPUID_LEN (8U)
95 
96 #if defined(DAC_COUNT) && DAC_COUNT > 0
97 
100 typedef struct {
101  DAC_TypeDef *dev;
102  CMU_Clock_TypeDef cmu;
103 } dac_conf_t;
104 
108 typedef struct {
109  uint8_t dev;
110  uint8_t index;
111  DAC_Ref_TypeDef ref;
112 } dac_chan_conf_t;
113 #endif
114 
119 #define HAVE_GPIO_T
120 typedef uint32_t gpio_t;
126 #define GPIO_UNDEF (0xffffffff)
127 
131 #define GPIO_PIN(x, y) ((gpio_t) ((x << 4) | y))
132 
136 #define GPIO_MODE(x, y) ((x << 1) | y)
137 
141 enum {
142 #if (_GPIO_PORT_A_PIN_COUNT > 0)
143  PA = gpioPortA,
144 #endif
145 #if (_GPIO_PORT_B_PIN_COUNT > 0)
146  PB = gpioPortB,
147 #endif
148 #if (_GPIO_PORT_C_PIN_COUNT > 0)
149  PC = gpioPortC,
150 #endif
151 #if (_GPIO_PORT_D_PIN_COUNT > 0)
152  PD = gpioPortD,
153 #endif
154 #if (_GPIO_PORT_E_PIN_COUNT > 0)
155  PE = gpioPortE,
156 #endif
157 #if (_GPIO_PORT_F_PIN_COUNT > 0)
158  PF = gpioPortF,
159 #endif
160 #if (_GPIO_PORT_G_PIN_COUNT > 0)
161  PG = gpioPortG,
162 #endif
163 #if (_GPIO_PORT_H_PIN_COUNT > 0)
164  PH = gpioPortH,
165 #endif
166 #if (_GPIO_PORT_I_PIN_COUNT > 0)
167  PI = gpioPortI,
168 #endif
169 #if (_GPIO_PORT_J_PIN_COUNT > 0)
170  PJ = gpioPortJ,
171 #endif
172 #if (_GPIO_PORT_K_PIN_COUNT > 0)
173  PK = gpioPortK
174 #endif
175 };
176 
177 #ifndef DOXYGEN
178 
182 #define HAVE_GPIO_MODE_T
183 typedef enum {
184  GPIO_IN = GPIO_MODE(gpioModeInput, 0),
185  GPIO_IN_PD = GPIO_MODE(gpioModeInputPull, 0),
186  GPIO_IN_PU = GPIO_MODE(gpioModeInputPull, 1),
187  GPIO_OUT = GPIO_MODE(gpioModePushPull, 0),
188  GPIO_OD = GPIO_MODE(gpioModeWiredAnd, 1),
189  GPIO_OD_PU = GPIO_MODE(gpioModeWiredAndPullUp, 1),
190 } gpio_mode_t;
197 #define HAVE_GPIO_FLANK_T
198 typedef enum {
199  GPIO_FALLING = 2,
200  GPIO_RISING = 1,
201  GPIO_BOTH = 3
202 } gpio_flank_t;
204 #endif /* ndef DOXYGEN */
205 
210 #define HAVE_HWCRYPTO_AES128
211 #ifdef AES_CTRL_AES256
212 #define HAVE_HWCRYPTO_AES256
213 #endif
214 #ifdef _SILICON_LABS_32B_SERIES_1
215 #define HAVE_HWCRYPTO_SHA1
216 #define HAVE_HWCRYPTO_SHA256
217 #endif
218 
220 #ifndef DOXYGEN
221 
225 #define HAVE_I2C_SPEED_T
226 typedef enum {
227  I2C_SPEED_LOW = 10000,
228  I2C_SPEED_NORMAL = 100000,
229  I2C_SPEED_FAST = 400000,
230  I2C_SPEED_FAST_PLUS = 1000000,
231  I2C_SPEED_HIGH = 3400000,
232 } i2c_speed_t;
234 #endif /* ndef DOXYGEN */
235 
239 typedef struct {
240  I2C_TypeDef *dev;
241  gpio_t sda_pin;
242  gpio_t scl_pin;
243  uint32_t loc;
244  CMU_Clock_TypeDef cmu;
246  uint32_t speed;
247 } i2c_conf_t;
248 
253 #define PERIPH_I2C_NEED_READ_REG
254 #define PERIPH_I2C_NEED_WRITE_REG
255 
257 #ifndef DOXYGEN
258 
262 #define HAVE_PWM_MODE_T
263 typedef enum {
264  PWM_LEFT = timerModeUp, /*< use left aligned PWM */
265  PWM_RIGHT = timerModeDown, /*< use right aligned PWM */
266  PWM_CENTER = timerModeUp /*< not supported, use left aligned */
267 } pwm_mode_t;
269 #endif /* ndef DOXYGEN */
270 
274 typedef struct {
275  uint8_t index;
276  gpio_t pin;
277  uint32_t loc;
279 
283 typedef struct {
284  TIMER_TypeDef *dev;
285  CMU_Clock_TypeDef cmu;
287  uint8_t channels;
289 } pwm_conf_t;
290 
291 #ifndef DOXYGEN
292 
296 #define HAVE_SPI_MODE_T
297 typedef enum {
298  SPI_MODE_0 = usartClockMode0,
299  SPI_MODE_1 = usartClockMode1,
300  SPI_MODE_2 = usartClockMode2,
301  SPI_MODE_3 = usartClockMode3
302 } spi_mode_t;
309 #define HAVE_SPI_CLK_T
310 typedef enum {
311  SPI_CLK_100KHZ = 100000,
312  SPI_CLK_400KHZ = 400000,
313  SPI_CLK_1MHZ = 1000000,
314  SPI_CLK_5MHZ = 5000000,
315  SPI_CLK_10MHZ = 10000000
316 } spi_clk_t;
318 #endif /* ndef DOXYGEN */
319 
323 typedef struct {
324  USART_TypeDef *dev;
325  gpio_t mosi_pin;
326  gpio_t miso_pin;
327  gpio_t clk_pin;
328  uint32_t loc;
329  CMU_Clock_TypeDef cmu;
331 } spi_dev_t;
332 
337 #define PERIPH_SPI_NEEDS_INIT_CS
338 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
339 #define PERIPH_SPI_NEEDS_TRANSFER_REG
340 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
341 
350 typedef struct {
351  TIMER_TypeDef *dev;
352  CMU_Clock_TypeDef cmu;
353 } timer_dev_t;
354 
355 typedef struct {
359 } timer_conf_t;
365 #ifndef DOXYGEN
366 
370 #define HAVE_UART_PARITY_T
371 typedef enum {
372  UART_PARITY_NONE = 0,
373  UART_PARITY_ODD = 1,
374  UART_PARITY_EVEN = 2,
375  UART_PARITY_MARK = 3,
376  UART_PARITY_SPACE = 4,
377 } uart_parity_t;
384 #define HAVE_UART_DATA_BITS_T
385 typedef enum {
386  UART_DATA_BITS_5 = 5,
387  UART_DATA_BITS_6 = 6,
388  UART_DATA_BITS_7 = 7,
389  UART_DATA_BITS_8 = 8,
397 #define HAVE_UART_STOP_BITS_T
398 typedef enum {
399  UART_STOP_BITS_1 = 2,
400  UART_STOP_BITS_2 = 4,
403 #endif /* ndef DOXYGEN */
404 
405 typedef struct {
406  void *dev;
407  gpio_t rx_pin;
408  gpio_t tx_pin;
409  uint32_t loc;
410  CMU_Clock_TypeDef cmu;
412 } uart_conf_t;
413 
417 #define PROVIDES_PM_LAYERED_OFF
418 
422 #define PM_NUM_MODES (2U)
423 
424 #ifdef __cplusplus
425 }
426 #endif
427 
428 #endif /* PERIPH_CPU_H */
429 
fast mode: ~400 kbit/s
Definition: i2c.h:184
CPOL=0, CPHA=1.
Definition: spi.h:159
SPI device configuration.
Definition: periph_cpu.h:323
configure as output in push-pull mode
Definition: gpio.h:117
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition: uart.h:141
high speed mode: ~3400 kbit/s
Definition: i2c.h:186
uint8_t index
TIMER channel to use.
Definition: periph_cpu.h:275
I2C configuration options.
Definition: periph_cpu.h:128
not supported
Definition: periph_cpu.h:144
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:245
TIMER_TypeDef * dev
TIMER device used.
Definition: periph_cpu.h:284
emit interrupt on rising flank
Definition: gpio.h:131
gpio_t mosi_pin
pin used for MOSI
Definition: periph_cpu.h:325
uint32_t loc
location of UART pins
Definition: periph_cpu.h:409
ADC resolution: 12 bit.
Definition: adc.h:97
PWM channel configuration.
Definition: periph_cpu.h:274
odd parity
Definition: uart.h:131
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:93
mark parity
Definition: uart.h:132
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:329
port A
Definition: periph_cpu.h:87
enum IRQn IRQn_Type
Interrupt Number Definition.
uart_stop_bits_t
Definition of possible stop bits lengths in a UART frame.
Definition: uart.h:153
port B
Definition: periph_cpu.h:88
CPOL=0, CPHA=0.
Definition: spi.h:158
gpio_t miso_pin
pin used for MISO
Definition: periph_cpu.h:326
Implementation specific CPU configuration options.
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:181
drive the SPI bus with 100KHz
Definition: spi.h:174
port C
Definition: periph_cpu.h:89
space parity
Definition: uart.h:133
drive the SPI bus with 400KHz
Definition: spi.h:175
uint8_t channels
the number of available channels
Definition: periph_cpu.h:287
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:411
PWM device configuration.
no parity
Definition: uart.h:129
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:74
emit interrupt on both flanks
Definition: gpio.h:132
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:244
5 data bits
Definition: uart.h:142
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:129
const pwm_chan_conf_t * channel
pointer to first channel config
Definition: periph_cpu.h:288
uint8_t dev
device index
Definition: periph_cpu.h:81
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
timer_dev_t timer
the higher numbered timer
Definition: periph_cpu.h:357
uint32_t loc
location of USART pins
Definition: periph_cpu.h:328
ADC_PosSel_TypeDef input
input channel
Definition: periph_cpu.h:85
ADC resolution: 14 bit.
Definition: adc.h:98
left aligned PWM
Definition: periph_cpu.h:142
uart_parity_t
Definition of possible parity modes.
Definition: uart.h:128
1 stop bit
Definition: uart.h:154
#define ADC_MODE(x, y)
Internal macro for combining ADC resolution (x) with number of shifts (y).
Definition: periph_cpu.h:45
even parity
Definition: uart.h:130
ADC resolution: 10 bit.
Definition: adc.h:96
7 data bits
Definition: uart.h:144
spi_clk_t
Available SPI clock speeds.
Definition: spi.h:173
CPOL=1, CPHA=1.
Definition: spi.h:161
port D
Definition: periph_cpu.h:90
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:352
2 stop bits
Definition: uart.h:155
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:286
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:73
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
gpio_t adc_conf_t
ADC configuration wrapper.
Definition: periph_cpu.h:313
ADC resolution: 16 bit.
Definition: adc.h:99
gpio_t pin
pin used for pwm
Definition: periph_cpu.h:276
IRQn_Type irq
number of the higher timer IRQ channel
Definition: periph_cpu.h:358
uint32_t loc
location of the pin
Definition: periph_cpu.h:277
drive the SPI bus with 5MHz
Definition: spi.h:177
ADC resolution: 8 bit.
Definition: adc.h:95
ADC_Ref_TypeDef reference
channel voltage reference
Definition: periph_cpu.h:87
timer_dev_t prescaler
the lower numbered neighboring timer
Definition: periph_cpu.h:356
ADC resolution: 6 bit.
Definition: adc.h:94
uint32_t speed
the bus speed
Definition: periph_cpu.h:246
drive the SPI bus with 10MHz
Definition: spi.h:178
emit interrupt on falling flank
Definition: gpio.h:130
Mutex for thread synchronization.
drive the SPI bus with 1MHz
Definition: spi.h:176
8 data bits
Definition: uart.h:145
#define ADC_MODE_UNDEF(x)
Internal define to note that resolution is not supported.
Definition: periph_cpu.h:50
6 data bits
Definition: uart.h:143
configure as input with pull-up resistor
Definition: gpio.h:116
#define GPIO_MODE(x, y)
Internal macro for combining pin mode (x) and pull-up/down (y).
Definition: periph_cpu.h:136
pwm_mode_t
Definition: periph_cpu.h:141
UART device configuration.
Definition: periph_cpu.h:166
gpio_mode_t
Available pin modes.
Definition: gpio.h:113
configure as input without pull resistor
Definition: gpio.h:114
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
DAC line configuration data.
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:410
uint32_t loc
location of I2C pins
Definition: periph_cpu.h:243
low speed mode: ~10 kbit/s
Definition: i2c.h:182
Define timer configuration values.
Definition: periph_cpu.h:350
TIMER_TypeDef * dev
Timer device used.
Definition: periph_cpu.h:351
configure as output in open-drain mode without pull resistor
Definition: gpio.h:118
CPOL=1, CPHA=0.
Definition: spi.h:160
gpio_t clk_pin
pin used for CLK
Definition: periph_cpu.h:327
normal mode: ~100 kbit/s
Definition: i2c.h:183
configure as input with pull-down resistor
Definition: gpio.h:115
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:285
right aligned PWM
Definition: periph_cpu.h:143
port F
Definition: periph_cpu.h:92
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:120
ADC channel configuration.
Definition: periph_cpu.h:80
USART_TypeDef * dev
USART device used.
Definition: periph_cpu.h:324
Timer configuration.
Definition: periph_cpu.h:286
port E
Definition: periph_cpu.h:91
ADC_AcqTime_TypeDef acq_time
channel acquisition time
Definition: periph_cpu.h:88
fast plus mode: ~1000 kbit/s
Definition: i2c.h:185
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:330
void * dev
UART, USART or LEUART device used.
Definition: periph_cpu.h:406