periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2017 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CPU_H
21 #define PERIPH_CPU_H
22 
23 #include "kernel_defines.h"
24 #include "mutex.h"
25 
26 #include "cpu_conf.h"
27 
28 #include "em_adc.h"
29 #include "em_cmu.h"
30 #include "em_device.h"
31 #include "em_gpio.h"
32 #include "em_timer.h"
33 #include "em_usart.h"
34 #if defined(_SILICON_LABS_32B_SERIES_0)
35 #include "em_dac.h"
36 #endif
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
46 #define ADC_MODE(x, y) ((y << 4) | x)
47 
51 #define ADC_MODE_UNDEF(x) (ADC_MODE(x, 15))
52 
53 #ifndef DOXYGEN
54 
58 #define HAVE_ADC_RES_T
59 typedef enum {
60  ADC_RES_6BIT = ADC_MODE(adcRes6Bit, 0),
61  ADC_RES_8BIT = ADC_MODE(adcRes8Bit, 0),
62  ADC_RES_10BIT = ADC_MODE(adcRes12Bit, 2),
63  ADC_RES_12BIT = ADC_MODE(adcRes12Bit, 0),
66 } adc_res_t;
68 #endif /* ndef DOXYGEN */
69 
73 typedef struct {
74  ADC_TypeDef *dev;
75  CMU_Clock_TypeDef cmu;
76 } adc_conf_t;
77 
81 typedef struct {
82  uint8_t dev;
83 #if defined(_SILICON_LABS_32B_SERIES_0)
84  ADC_SingleInput_TypeDef input;
85 #elif defined(_SILICON_LABS_32B_SERIES_1)
86  ADC_PosSel_TypeDef input;
87 #endif
88  ADC_Ref_TypeDef reference;
89  ADC_AcqTime_TypeDef acq_time;
91 
95 #define CPUID_LEN (8U)
96 
100 #define CLOCK_CORECLOCK SystemCoreClock
101 
102 #if defined(DAC_COUNT) && DAC_COUNT > 0
103 
106 typedef struct {
107  DAC_TypeDef *dev;
108  CMU_Clock_TypeDef cmu;
109 } dac_conf_t;
110 
114 typedef struct {
115  uint8_t dev;
116  uint8_t index;
117  DAC_Ref_TypeDef ref;
118 } dac_chan_conf_t;
119 #endif
120 
125 #define HAVE_GPIO_T
126 typedef uint32_t gpio_t;
132 #define GPIO_UNDEF (0xffffffff)
133 
137 #define GPIO_PIN(x, y) ((gpio_t) ((x << 4) | y))
138 
142 #define GPIO_MODE(x, y) ((x << 1) | y)
143 
147 enum {
148 #if (_GPIO_PORT_A_PIN_COUNT > 0)
149  PA = gpioPortA,
150 #endif
151 #if (_GPIO_PORT_B_PIN_COUNT > 0)
152  PB = gpioPortB,
153 #endif
154 #if (_GPIO_PORT_C_PIN_COUNT > 0)
155  PC = gpioPortC,
156 #endif
157 #if (_GPIO_PORT_D_PIN_COUNT > 0)
158  PD = gpioPortD,
159 #endif
160 #if (_GPIO_PORT_E_PIN_COUNT > 0)
161  PE = gpioPortE,
162 #endif
163 #if (_GPIO_PORT_F_PIN_COUNT > 0)
164  PF = gpioPortF,
165 #endif
166 #if (_GPIO_PORT_G_PIN_COUNT > 0)
167  PG = gpioPortG,
168 #endif
169 #if (_GPIO_PORT_H_PIN_COUNT > 0)
170  PH = gpioPortH,
171 #endif
172 #if (_GPIO_PORT_I_PIN_COUNT > 0)
173  PI = gpioPortI,
174 #endif
175 #if (_GPIO_PORT_J_PIN_COUNT > 0)
176  PJ = gpioPortJ,
177 #endif
178 #if (_GPIO_PORT_K_PIN_COUNT > 0)
179  PK = gpioPortK
180 #endif
181 };
182 
183 #ifndef DOXYGEN
184 
188 #define HAVE_GPIO_MODE_T
189 typedef enum {
190  GPIO_IN = GPIO_MODE(gpioModeInput, 0),
191  GPIO_IN_PD = GPIO_MODE(gpioModeInputPull, 0),
192  GPIO_IN_PU = GPIO_MODE(gpioModeInputPull, 1),
193  GPIO_OUT = GPIO_MODE(gpioModePushPull, 0),
194  GPIO_OD = GPIO_MODE(gpioModeWiredAnd, 1),
195  GPIO_OD_PU = GPIO_MODE(gpioModeWiredAndPullUp, 1),
196 } gpio_mode_t;
203 #define HAVE_GPIO_FLANK_T
204 typedef enum {
205  GPIO_FALLING = 2,
206  GPIO_RISING = 1,
207  GPIO_BOTH = 3
208 } gpio_flank_t;
210 #endif /* ndef DOXYGEN */
211 
216 #define HAVE_HWCRYPTO_AES128
217 #ifdef AES_CTRL_AES256
218 #define HAVE_HWCRYPTO_AES256
219 #endif
220 #if defined(_SILICON_LABS_32B_SERIES_1)
221 #define HAVE_HWCRYPTO_SHA1
222 #define HAVE_HWCRYPTO_SHA256
223 #endif
224 
226 #ifndef DOXYGEN
227 
231 #define HAVE_I2C_SPEED_T
232 typedef enum {
233  I2C_SPEED_LOW = 10000,
234  I2C_SPEED_NORMAL = 100000,
235  I2C_SPEED_FAST = 400000,
236  I2C_SPEED_FAST_PLUS = 1000000,
237  I2C_SPEED_HIGH = 3400000,
238 } i2c_speed_t;
240 #endif /* ndef DOXYGEN */
241 
245 typedef struct {
246  I2C_TypeDef *dev;
247  gpio_t sda_pin;
248  gpio_t scl_pin;
249  uint32_t loc;
250  CMU_Clock_TypeDef cmu;
252  uint32_t speed;
253 } i2c_conf_t;
254 
259 #define PERIPH_I2C_NEED_READ_REG
260 #define PERIPH_I2C_NEED_WRITE_REG
261 
263 #ifndef DOXYGEN
264 
268 #define HAVE_PWM_MODE_T
269 typedef enum {
270  PWM_LEFT = timerModeUp, /*< use left aligned PWM */
271  PWM_RIGHT = timerModeDown, /*< use right aligned PWM */
272  PWM_CENTER = timerModeUp /*< not supported, use left aligned */
273 } pwm_mode_t;
275 #endif /* ndef DOXYGEN */
276 
280 typedef struct {
281  uint8_t index;
282  gpio_t pin;
283  uint32_t loc;
285 
289 typedef struct {
290  TIMER_TypeDef *dev;
291  CMU_Clock_TypeDef cmu;
293  uint8_t channels;
295 } pwm_conf_t;
296 
297 #ifndef DOXYGEN
298 
302 #define HAVE_SPI_MODE_T
303 typedef enum {
304  SPI_MODE_0 = usartClockMode0,
305  SPI_MODE_1 = usartClockMode1,
306  SPI_MODE_2 = usartClockMode2,
307  SPI_MODE_3 = usartClockMode3
308 } spi_mode_t;
315 #define HAVE_SPI_CLK_T
316 typedef enum {
317  SPI_CLK_100KHZ = 100000,
318  SPI_CLK_400KHZ = 400000,
319  SPI_CLK_1MHZ = 1000000,
320  SPI_CLK_5MHZ = 5000000,
321  SPI_CLK_10MHZ = 10000000
322 } spi_clk_t;
324 #endif /* ndef DOXYGEN */
325 
329 typedef struct {
330  USART_TypeDef *dev;
331  gpio_t mosi_pin;
332  gpio_t miso_pin;
333  gpio_t clk_pin;
334  uint32_t loc;
335  CMU_Clock_TypeDef cmu;
337 } spi_dev_t;
338 
343 #define PERIPH_SPI_NEEDS_INIT_CS
344 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
345 #define PERIPH_SPI_NEEDS_TRANSFER_REG
346 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
347 
356 typedef struct {
357  void *dev;
358  CMU_Clock_TypeDef cmu;
359 } timer_dev_t;
360 
361 typedef struct {
365  uint8_t channel_numof;
366 } timer_conf_t;
373 #ifndef CONFIG_EFM32_XTIMER_USE_LETIMER
374 #define CONFIG_EFM32_XTIMER_USE_LETIMER 0
375 #endif
376 
377 
381 #ifndef DOXYGEN
382 
386 #define HAVE_UART_PARITY_T
387 typedef enum {
388  UART_PARITY_NONE = 0,
389  UART_PARITY_ODD = 1,
390  UART_PARITY_EVEN = 2,
391  UART_PARITY_MARK = 3,
392  UART_PARITY_SPACE = 4,
393 } uart_parity_t;
400 #define HAVE_UART_DATA_BITS_T
401 typedef enum {
402  UART_DATA_BITS_5 = 5,
403  UART_DATA_BITS_6 = 6,
404  UART_DATA_BITS_7 = 7,
405  UART_DATA_BITS_8 = 8,
413 #define HAVE_UART_STOP_BITS_T
414 typedef enum {
415  UART_STOP_BITS_1 = 2,
416  UART_STOP_BITS_2 = 4,
419 #endif /* ndef DOXYGEN */
420 
421 typedef struct {
422  void *dev;
423  gpio_t rx_pin;
424  gpio_t tx_pin;
425  uint32_t loc;
426  CMU_Clock_TypeDef cmu;
428 } uart_conf_t;
429 
433 #define PROVIDES_PM_LAYERED_OFF
434 
438 #define PM_NUM_MODES (2U)
439 
440 #ifdef __cplusplus
441 }
442 #endif
443 
444 #endif /* PERIPH_CPU_H */
445 
fast mode: ~400 kbit/s
Definition: i2c.h:178
CPOL=0, CPHA=1.
Definition: spi.h:159
port B
Definition: periph_cpu.h:93
SPI device configuration.
Definition: periph_cpu.h:329
configure as output in push-pull mode
Definition: gpio.h:122
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition: uart.h:139
high speed mode: ~3400 kbit/s
Definition: i2c.h:180
uint8_t index
TIMER channel to use.
Definition: periph_cpu.h:281
I2C configuration options.
Definition: periph_cpu.h:128
not supported
Definition: periph_cpu.h:162
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:251
TIMER_TypeDef * dev
TIMER device used.
Definition: periph_cpu.h:290
emit interrupt on rising flank
Definition: periph_cpu.h:82
gpio_t mosi_pin
pin used for MOSI
Definition: periph_cpu.h:331
uint32_t loc
location of UART pins
Definition: periph_cpu.h:425
ADC resolution: 12 bit.
Definition: adc.h:97
port C
Definition: periph_cpu.h:94
PWM channel configuration.
Definition: periph_cpu.h:280
odd parity
Definition: uart.h:129
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:93
mark parity
Definition: uart.h:130
drive the SPI bus with 100KHz
Definition: periph_cpu.h:636
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:335
drive the SPI bus with 400KHz
Definition: periph_cpu.h:637
enum IRQn IRQn_Type
Interrupt Number Definition.
uart_stop_bits_t
Definition of possible stop bits lengths in a UART frame.
Definition: uart.h:151
port D
Definition: periph_cpu.h:95
uint32_t spi_clk_t
SPI clock type.
Definition: periph_cpu.h:646
CPOL=0, CPHA=0.
Definition: spi.h:158
drive the SPI bus with 1MHz
Definition: periph_cpu.h:638
gpio_t miso_pin
pin used for MISO
Definition: periph_cpu.h:332
Implementation specific CPU configuration options.
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:175
space parity
Definition: uart.h:131
uint8_t channels
the number of available channels
Definition: periph_cpu.h:293
gpio_flank_t
Definition: periph_cpu.h:80
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:427
PWM device configuration.
port E
Definition: periph_cpu.h:96
no parity
Definition: uart.h:127
drive the SPI bus with 5MHz
Definition: periph_cpu.h:639
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:75
emit interrupt on both flanks
Definition: periph_cpu.h:83
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:250
5 data bits
Definition: uart.h:140
const pwm_chan_conf_t * channel
pointer to first channel config
Definition: periph_cpu.h:294
uint8_t dev
device index
Definition: periph_cpu.h:82
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
timer_dev_t timer
the higher numbered timer
Definition: periph_cpu.h:363
uint32_t loc
location of USART pins
Definition: periph_cpu.h:334
port F
Definition: periph_cpu.h:97
ADC resolution: 14 bit.
Definition: adc.h:98
left aligned PWM
Definition: periph_cpu.h:160
uart_parity_t
Definition of possible parity modes.
Definition: uart.h:126
1 stop bit
Definition: uart.h:152
#define ADC_MODE(x, y)
Internal macro for combining ADC resolution (x) with number of shifts (y).
Definition: periph_cpu.h:46
even parity
Definition: uart.h:128
ADC resolution: 10 bit.
Definition: adc.h:96
7 data bits
Definition: uart.h:142
CPOL=1, CPHA=1.
Definition: spi.h:161
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:358
2 stop bits
Definition: uart.h:153
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:292
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
gpio_t adc_conf_t
ADC configuration wrapper.
Definition: periph_cpu.h:315
void * dev
TIMER_TypeDef or LETIMER_TypeDef device used.
Definition: periph_cpu.h:357
ADC resolution: 16 bit.
Definition: adc.h:99
gpio_t pin
pin used for pwm
Definition: periph_cpu.h:282
IRQn_Type irq
number of the higher timer IRQ channel
Definition: periph_cpu.h:364
uint32_t loc
location of the pin
Definition: periph_cpu.h:283
ADC resolution: 8 bit.
Definition: adc.h:95
ADC_Ref_TypeDef reference
channel voltage reference
Definition: periph_cpu.h:88
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:74
timer_dev_t prescaler
the lower neighboring timer (not initialized for LETIMER)
Definition: periph_cpu.h:362
ADC resolution: 6 bit.
Definition: adc.h:94
uint32_t speed
the bus speed
Definition: periph_cpu.h:252
emit interrupt on falling flank
Definition: periph_cpu.h:81
Mutex for thread synchronization.
8 data bits
Definition: uart.h:143
#define ADC_MODE_UNDEF(x)
Internal define to note that resolution is not supported.
Definition: periph_cpu.h:51
6 data bits
Definition: uart.h:141
configure as input with pull-up resistor
Definition: gpio.h:121
#define GPIO_MODE(x, y)
Internal macro for combining pin mode (x) and pull-up/down (y).
Definition: periph_cpu.h:142
pwm_mode_t
Definition: periph_cpu.h:159
Common macros and compiler attributes/pragmas configuration.
UART device configuration.
Definition: periph_cpu.h:166
configure as input without pull resistor
Definition: gpio.h:119
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:246
port A
Definition: periph_cpu.h:92
DAC line configuration data.
Definition: periph_cpu.h:502
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:426
uint32_t loc
location of I2C pins
Definition: periph_cpu.h:249
drive the SPI bus with 10MHz
Definition: periph_cpu.h:640
uint8_t channel_numof
number of channels per timer
Definition: periph_cpu.h:365
low speed mode: ~10 kbit/s
Definition: i2c.h:176
Define timer configuration values.
Definition: periph_cpu.h:356
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
CPOL=1, CPHA=0.
Definition: spi.h:160
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:70
gpio_t clk_pin
pin used for CLK
Definition: periph_cpu.h:333
normal mode: ~100 kbit/s
Definition: i2c.h:177
configure as input with pull-down resistor
Definition: gpio.h:120
CMU_Clock_TypeDef cmu
the device CMU channel
Definition: periph_cpu.h:291
right aligned PWM
Definition: periph_cpu.h:161
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
ADC channel configuration.
Definition: periph_cpu.h:81
USART_TypeDef * dev
USART device used.
Definition: periph_cpu.h:330
Timer configuration.
Definition: periph_cpu.h:288
ADC_AcqTime_TypeDef acq_time
channel acquisition time
Definition: periph_cpu.h:89
fast plus mode: ~1000 kbit/s
Definition: i2c.h:179
IRQn_Type irq
the devices base IRQ channel
Definition: periph_cpu.h:336
void * dev
UART, USART or LEUART device used.
Definition: periph_cpu.h:422