23 #ifndef PERIPH_CPU_COMMON_H 24 #define PERIPH_CPU_COMMON_H 36 #define CPUID_LEN (4U) 52 #define GPIO_UNDEF (0xff) 57 #define GPIO_PIN(x, y) ((x << 4) | y) 69 #define HAVE_GPIO_FLANK_T 83 #define PERIPH_SPI_NEEDS_INIT_CS 84 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE 85 #define PERIPH_SPI_NEEDS_TRANSFER_REG 86 #define PERIPH_SPI_NEEDS_TRANSFER_REGS 96 #define SPI_MODE_SEL(pol, pha) ((pol << 3) | (pha << 2)) 105 #define HAVE_SPI_MODE_T 120 #define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0) 128 #define HAVE_SPI_CLK_T 163 #define EEPROM_CLEAR_BYTE (0xff) 169 #define NWDT_TIME_LOWER_LIMIT (1) 170 #define NWDT_TIME_UPPER_LIMIT (8192U) 176 #define WDT_HAS_STOP (1) 183 #if defined(SCCR0) && !defined(RTT_BACKEND_SC) 184 #define RTT_BACKEND_SC (1) 189 #ifndef RTT_MAX_VALUE 190 #define RTT_MAX_VALUE (0xFFFFFFFFUL) 193 #ifndef RTT_FREQUENCY 194 #define RTT_FREQUENCY (62500UL) 199 #ifndef RTT_MAX_VALUE 200 #define RTT_MAX_VALUE (0x00FFFFFF) 203 #ifndef RTT_FREQUENCY 204 #define RTT_FREQUENCY (1024U)
emit interrupt on rising flank
timer_div_t
Bitmasks indicating which are the possible dividers for a timer.
1/{1,8,32,64,128,256,1024}
drive the SPI bus with 100KHz
mini_timer_t * dev
Timer used.
drive the SPI bus with 400KHz
timer_div_t div
Timer divider mask.
emit interrupt on both flanks
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
spi_clk_t
Available SPI clock speeds.
unsigned int gpio_t
GPIO type identifier.
drive the SPI bus with 5MHz
drive the SPI bus with 10MHz
emit interrupt on falling flank
drive the SPI bus with 1MHz