periph_cpu_common.h
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1 /*
2  * Copyright (C) 2015 HAW Hamburg
3  * 2016 Freie Universit├Ąt Berlin
4  * 2016 INRIA
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef PERIPH_CPU_COMMON_H
24 #define PERIPH_CPU_COMMON_H
25 
26 #include "cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 #define CPUID_LEN (4U)
37 
39 #ifndef DOXYGEN
40 
44 #define HAVE_GPIO_T
45 typedef uint8_t gpio_t;
47 #endif
48 
52 #define GPIO_UNDEF (0xff)
53 
57 #define GPIO_PIN(x, y) ((x << 4) | y)
58 
59 #ifndef DOXYGEN
60 
69 #define HAVE_GPIO_FLANK_T
70 typedef enum {
71  GPIO_LOW,
72  GPIO_BOTH,
73  GPIO_FALLING,
74  GPIO_RISING,
75 } gpio_flank_t;
77 #endif /* ndef DOXYGEN */
78 
83 #define PERIPH_SPI_NEEDS_INIT_CS
84 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
85 #define PERIPH_SPI_NEEDS_TRANSFER_REG
86 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
87 
89 #ifndef DOXYGEN
90 
96 #define SPI_MODE_SEL(pol, pha) ((pol << 3) | (pha << 2))
97 
105 #define HAVE_SPI_MODE_T
106 typedef enum {
107  SPI_MODE_0 = SPI_MODE_SEL(0, 0),
108  SPI_MODE_1 = SPI_MODE_SEL(0, 1),
109  SPI_MODE_2 = SPI_MODE_SEL(1, 0),
110  SPI_MODE_3 = SPI_MODE_SEL(1, 1)
111 } spi_mode_t;
120 #define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
121 
128 #define HAVE_SPI_CLK_T
129 typedef enum {
130  SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1),
131  SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0),
132  SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1),
133  SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0),
134  SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0)
135 } spi_clk_t;
137 #endif /* ndef DOXYGEN */
138 
143 typedef enum {
146 } timer_div_t;
153 typedef struct {
155  gpio_t pin_ch[2];
157 } pwm_conf_t;
163 #define EEPROM_CLEAR_BYTE (0xff)
164 
169 #define NWDT_TIME_LOWER_LIMIT (1)
170 #define NWDT_TIME_UPPER_LIMIT (8192U)
171 
176 #define WDT_HAS_STOP (1)
177 
183 #if defined(SCCR0) && !defined(RTT_BACKEND_SC)
184 #define RTT_BACKEND_SC (1)
185 #endif
186 
187 #if RTT_BACKEND_SC
188 /* For MCU with MAC symbol counter */
189 #ifndef RTT_MAX_VALUE
190 #define RTT_MAX_VALUE (0xFFFFFFFFUL) /* 32-bit timer */
191 #endif
192 
193 #ifndef RTT_FREQUENCY
194 #define RTT_FREQUENCY (62500UL) /* in Hz. */
195 #endif
196 
197 #else
198 /* For MCU without MAC symbol counter */
199 #ifndef RTT_MAX_VALUE
200 #define RTT_MAX_VALUE (0x00FFFFFF) /* 24-bit timer */
201 #endif
202 /* possible values: 32, 128, 256, 512, 1024, 4096, 32768 */
203 #ifndef RTT_FREQUENCY
204 #define RTT_FREQUENCY (1024U) /* in Hz. */
205 #endif
206 #endif
207 
209 #ifdef __cplusplus
210 }
211 #endif
212 
213 #endif /* PERIPH_CPU_COMMON_H */
214 
1/{1,8,64,128,1024}
CPOL=0, CPHA=1.
Definition: spi.h:159
emit interrupt on rising flank
Definition: gpio.h:131
timer_div_t
Bitmasks indicating which are the possible dividers for a timer.
1/{1,8,32,64,128,256,1024}
CPOL=0, CPHA=0.
Definition: spi.h:158
drive the SPI bus with 100KHz
Definition: spi.h:174
mini_timer_t * dev
Timer used.
8-bit timer register map
drive the SPI bus with 400KHz
Definition: spi.h:175
timer_div_t div
Timer divider mask.
PWM configuration.
emit interrupt on both flanks
Definition: gpio.h:132
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:129
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
spi_clk_t
Available SPI clock speeds.
Definition: spi.h:173
CPOL=1, CPHA=1.
Definition: spi.h:161
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
drive the SPI bus with 5MHz
Definition: spi.h:177
drive the SPI bus with 10MHz
Definition: spi.h:178
emit interrupt on falling flank
Definition: gpio.h:130
drive the SPI bus with 1MHz
Definition: spi.h:176
CPOL=1, CPHA=0.
Definition: spi.h:160