periph_cpu_common.h File Reference

CPU specific definitions for internal peripheral handling. More...

Detailed Description

#include "cpu.h"
+ Include dependency graph for periph_cpu_common.h:

Go to the source code of this file.

Data Structures

struct  pwm_conf_t
 PWM configuration. More...
 

Macros

#define SPI_MODE_SEL(pol, pha)   ((pol << 3) | (pha << 2))
 SPI mode select macro. More...
 
#define SPI_CLK_SEL(s2x, pr1, pr0)   ((s2x << 2) | (pr1 << 1) | pr0)
 SPI speed selection macro. More...
 
#define EEPROM_CLEAR_BYTE   (0xff)
 EEPROM clear byte.
 
#define GPIO_UNDEF   (0xff)
 Definition of a fitting UNDEF value.
 
#define GPIO_PIN(x, y)   ((x << 4) | y)
 Define a CPU specific GPIO pin generator macro.
 
#define HAVE_GPIO_FLANK_T
 Override the GPIO flanks. More...
 
enum  gpio_flank_t {
  GPIO_LOW, GPIO_BOTH, GPIO_FALLING, GPIO_RISING,
  GPIO_NONE = 0, GPIO_RISING = 1, GPIO_FALLING = 2, GPIO_BOTH = 3,
  GPIO_LOW = 4, GPIO_HIGH = 5, GPIO_FALLING = 0, GPIO_RISING = 1,
  GPIO_BOTH = 2
}
 
#define PERIPH_SPI_NEEDS_INIT_CS
 Use some common SPI functions.
 
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
 
#define PERIPH_SPI_NEEDS_TRANSFER_REG
 
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 
#define HAVE_SPI_MODE_T
 Override the SPI mode values. More...
 
enum  spi_mode_t {
  SPI_MODE_0 = SPI_MODE_SEL(0, 0), SPI_MODE_1 = SPI_MODE_SEL(0, 1), SPI_MODE_2 = SPI_MODE_SEL(1, 0), SPI_MODE_3 = SPI_MODE_SEL(1, 1),
  SPI_MODE_0 = 0, SPI_MODE_1 = (SSI_CR0_SPH), SPI_MODE_2 = (SSI_CR0_SPO), SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH),
  SPI_MODE_0 = SSI_FRF_MOTO_MODE_0, SPI_MODE_1 = SSI_FRF_MOTO_MODE_1, SPI_MODE_2 = SSI_FRF_MOTO_MODE_2, SPI_MODE_3 = SSI_FRF_MOTO_MODE_0,
  SPI_MODE_0 = 0, SPI_MODE_1 = SPI_CONFIG_CPHA_Msk, SPI_MODE_2 = SPI_CONFIG_CPOL_Msk, SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk),
  SPI_MODE_0 = 0x0, SPI_MODE_1 = 0x1, SPI_MODE_2 = 0x2, SPI_MODE_3 = 0x3,
  SPI_MODE_0 = (SPI_CSR_NCPHA), SPI_MODE_1 = (0), SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA), SPI_MODE_3 = (SPI_CSR_CPOL),
  SPI_MODE_0 = 0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3
}
 
#define HAVE_SPI_CLK_T
 Override SPI speed values. More...
 
enum  spi_clk_t {
  SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1), SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0), SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1), SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0),
  SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0), SPI_CLK_100KHZ = 0, SPI_CLK_400KHZ = 1, SPI_CLK_1MHZ = 2,
  SPI_CLK_5MHZ = 3, SPI_CLK_10MHZ = 4, SPI_CLK_100KHZ = 100000, SPI_CLK_400KHZ = 400000,
  SPI_CLK_1MHZ = 1000000, SPI_CLK_4MHZ = 4000000, SPI_CLK_5MHZ = 5000000, SPI_CLK_10MHZ = 10000000,
  SPI_CLK_100KHZ = 100, SPI_CLK_400KHZ = 400, SPI_CLK_1MHZ = 1000, SPI_CLK_5MHZ = 5000,
  SPI_CLK_10MHZ = 10000, SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125, SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500, SPI_CLK_1MHZ = SPI_FREQUENCY_FREQUENCY_M1,
  SPI_CLK_5MHZ = SPI_FREQUENCY_FREQUENCY_M4, SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8, SPI_CLK_100KHZ = 100000U, SPI_CLK_400KHZ = 400000U,
  SPI_CLK_1MHZ = 1000000U, SPI_CLK_5MHZ = 5000000U, SPI_CLK_10MHZ = 10000000U, SPI_CLK_100KHZ = (100000),
  SPI_CLK_400KHZ = (400000), SPI_CLK_1MHZ = (1000000), SPI_CLK_5MHZ = (5000000), SPI_CLK_10MHZ = (10000000),
  SPI_CLK_100KHZ = 0, SPI_CLK_400KHZ, SPI_CLK_1MHZ, SPI_CLK_5MHZ,
  SPI_CLK_10MHZ
}
 
enum  timer_div_t { TIMER_DIV1_8_64_128_1024 = 0x549, TIMER_DIV1_8_32_64_128_256_1024 = 0x5E9 }
 Bitmasks indicating which are the possible dividers for a timer. More...
 

Macro Definition Documentation

◆ HAVE_GPIO_FLANK_T

#define HAVE_GPIO_FLANK_T

Override the GPIO flanks.

This device has an additional mode in which the interrupt is triggered when the pin is low.

Enumeration order is important, do not modify.

Definition at line 61 of file periph_cpu_common.h.

◆ HAVE_SPI_CLK_T

#define HAVE_SPI_CLK_T

Override SPI speed values.

We assume a master clock speed of 16MHz here.

Definition at line 118 of file periph_cpu_common.h.

◆ HAVE_SPI_MODE_T

#define HAVE_SPI_MODE_T

Override the SPI mode values.

As the mode is set in bit 3 and 2 of the configuration register, we put the correct configuration there

Definition at line 95 of file periph_cpu_common.h.

◆ SPI_CLK_SEL

#define SPI_CLK_SEL (   s2x,
  pr1,
  pr0 
)    ((s2x << 2) | (pr1 << 1) | pr0)

SPI speed selection macro.

We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR prescaler bits, while bit2 holds the SPI2X bit.

Definition at line 110 of file periph_cpu_common.h.

◆ SPI_MODE_SEL

#define SPI_MODE_SEL (   pol,
  pha 
)    ((pol << 3) | (pha << 2))

SPI mode select macro.

The polarity is determined by bit 3 in the configuration register, the phase by bit 2.

Definition at line 86 of file periph_cpu_common.h.

Enumeration Type Documentation

◆ gpio_flank_t

Enumerator
GPIO_LOW 

emit interrupt when pin low

GPIO_BOTH 

emit interrupt on both flanks

GPIO_FALLING 

emit interrupt on falling flank

GPIO_RISING 

emit interrupt on rising flank

GPIO_RISING 

emit interrupt on rising flank

GPIO_FALLING 

emit interrupt on falling flank

GPIO_BOTH 

emit interrupt on both flanks

GPIO_LOW 

emit interrupt on low level

GPIO_HIGH 

emit interrupt on low level

GPIO_FALLING 

emit interrupt on falling flank

GPIO_RISING 

emit interrupt on rising flank

GPIO_BOTH 

emit interrupt on both flanks

Definition at line 62 of file periph_cpu_common.h.

◆ spi_clk_t

enum spi_clk_t
Enumerator
SPI_CLK_100KHZ 

16/128 -> 125KHz

SPI_CLK_400KHZ 

16/32 -> 500KHz

SPI_CLK_1MHZ 

16/16 -> 1MHz

SPI_CLK_5MHZ 

16/4 -> 4MHz

SPI_CLK_10MHZ 

16/2 -> 8MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_4MHZ 

drive the SPI bus with 4MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

100KHz

SPI_CLK_400KHZ 

400KHz

SPI_CLK_1MHZ 

1MHz

SPI_CLK_5MHZ 

5MHz

SPI_CLK_10MHZ 

10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

100KHz

SPI_CLK_400KHZ 

400KHz

SPI_CLK_1MHZ 

1MHz

SPI_CLK_5MHZ 

5MHz

SPI_CLK_10MHZ 

10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

Definition at line 119 of file periph_cpu_common.h.

◆ spi_mode_t

enum spi_mode_t
Enumerator
SPI_MODE_0 

mode 0

SPI_MODE_1 

mode 1

SPI_MODE_2 

mode 2

SPI_MODE_3 

mode 3

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

Definition at line 96 of file periph_cpu_common.h.

◆ timer_div_t

Bitmasks indicating which are the possible dividers for a timer.

Enumerator
TIMER_DIV1_8_64_128_1024 

1/{1,8,64,128,1024}

TIMER_DIV1_8_32_64_128_256_1024 

1/{1,8,32,64,128,256,1024}

Definition at line 132 of file periph_cpu_common.h.