periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 #include "cfg_timer_tim5.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
35 #define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
36 /*
37  * 0: no external low speed crystal available,
38  * 1: external crystal available (always 32.768kHz)
39  *
40  * LSE might not be available by default in early (C-01) Nucleo boards.
41  * For newer revisions, an LSE crystal is present and CLOCK_LSE can be set to 1
42  * if one wants to use it.
43  */
44 #ifndef CLOCK_LSE
45 #define CLOCK_LSE (0)
46 #endif
47 /* configuration of PLL prescaler and multiply values */
48 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
49 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
50 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
51 /* configuration of peripheral bus clock prescalers */
52 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
53 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
54 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
55 /* configuration of flash access cycles */
56 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
57 
58 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
59 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
60 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
61 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
62 
68 #ifdef MODULE_PERIPH_DMA
69 static const dma_conf_t dma_config[] = {
70  { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX / USART3_TX */
71  { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
72  { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
73  { .stream = 4 }, /* DMA1 Channel 4 - USART1_TX */
74 };
75 
76 #define DMA_0_ISR isr_dma1_ch2
77 #define DMA_1_ISR isr_dma1_ch3
78 #define DMA_2_ISR isr_dma1_ch7
79 #define DMA_3_ISR isr_dma1_ch4
80 
81 #define DMA_NUMOF ARRAY_SIZE(dma_config)
82 #endif
83 
89 static const uart_conf_t uart_config[] = {
90  {
91  .dev = USART2,
92  .rcc_mask = RCC_APB1ENR_USART2EN,
93  .rx_pin = GPIO_PIN(PORT_A, 3),
94  .tx_pin = GPIO_PIN(PORT_A, 2),
95  .rx_af = GPIO_AF7,
96  .tx_af = GPIO_AF7,
97  .bus = APB1,
98  .irqn = USART2_IRQn,
99 #ifdef MODULE_PERIPH_DMA
100  .dma = 2,
101  .dma_chan = 2
102 #endif
103  },
104  {
105  .dev = USART1,
106  .rcc_mask = RCC_APB2ENR_USART1EN,
107  .rx_pin = GPIO_PIN(PORT_A, 10),
108  .tx_pin = GPIO_PIN(PORT_A, 9),
109  .rx_af = GPIO_AF7,
110  .tx_af = GPIO_AF7,
111  .bus = APB2,
112  .irqn = USART1_IRQn,
113 #ifdef MODULE_PERIPH_DMA
114  .dma = 3,
115  .dma_chan = 2
116 #endif
117  },
118  {
119  .dev = USART3,
120  .rcc_mask = RCC_APB1ENR_USART3EN,
121  .rx_pin = GPIO_PIN(PORT_C, 11),
122  .tx_pin = GPIO_PIN(PORT_C, 10),
123  .rx_af = GPIO_AF7,
124  .tx_af = GPIO_AF7,
125  .bus = APB1,
126  .irqn = USART3_IRQn,
127 #ifdef MODULE_PERIPH_DMA
128  .dma = 0,
129  .dma_chan = 2
130 #endif
131  },
132 };
133 
134 #define UART_0_ISR (isr_usart2)
135 #define UART_1_ISR (isr_usart1)
136 #define UART_2_ISR (isr_usart3)
137 
138 #define UART_NUMOF ARRAY_SIZE(uart_config)
139 
145 static const pwm_conf_t pwm_config[] = {
146  {
147  .dev = TIM2,
148  .rcc_mask = RCC_APB1ENR_TIM2EN,
149  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
150  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
151  { .pin = GPIO_UNDEF, .cc_chan = 0 },
152  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
153  .af = GPIO_AF1,
154  .bus = APB1
155  },
156  {
157  .dev = TIM3,
158  .rcc_mask = RCC_APB1ENR_TIM3EN,
159  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
160  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
161  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
162  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
163  .af = GPIO_AF2,
164  .bus = APB1
165  }
166 };
167 
168 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
169 
178 static const uint8_t spi_divtable[2][5] = {
179  { /* for APB1 @ 32000000Hz */
180  7, /* -> 125000Hz */
181  5, /* -> 500000Hz */
182  4, /* -> 1000000Hz */
183  2, /* -> 4000000Hz */
184  1 /* -> 8000000Hz */
185  },
186  { /* for APB2 @ 32000000Hz */
187  7, /* -> 125000Hz */
188  5, /* -> 500000Hz */
189  4, /* -> 1000000Hz */
190  2, /* -> 4000000Hz */
191  1 /* -> 8000000Hz */
192  }
193 };
194 
195 static const spi_conf_t spi_config[] = {
196  {
197  .dev = SPI1,
198  .mosi_pin = GPIO_PIN(PORT_A, 7),
199  .miso_pin = GPIO_PIN(PORT_A, 6),
200  .sclk_pin = GPIO_PIN(PORT_A, 5),
201  .cs_pin = GPIO_UNDEF,
202  .mosi_af = GPIO_AF5,
203  .miso_af = GPIO_AF5,
204  .sclk_af = GPIO_AF5,
205  .cs_af = GPIO_AF5,
206  .rccmask = RCC_APB2ENR_SPI1EN,
207  .apbbus = APB2,
208 #ifdef MODULE_PERIPH_DMA
209  .tx_dma = 1,
210  .tx_dma_chan = 1,
211  .rx_dma = 0,
212  .rx_dma_chan = 1,
213 #endif
214  }
215 };
216 
217 #define SPI_NUMOF ARRAY_SIZE(spi_config)
218 
224 static const i2c_conf_t i2c_config[] = {
225  {
226  .dev = I2C1,
227  .speed = I2C_SPEED_NORMAL,
228  .scl_pin = GPIO_PIN(PORT_B, 8),
229  .sda_pin = GPIO_PIN(PORT_B, 9),
230  .scl_af = GPIO_AF4,
231  .sda_af = GPIO_AF4,
232  .bus = APB1,
233  .rcc_mask = RCC_APB1ENR_I2C1EN,
234  .clk = CLOCK_APB1,
235  .irqn = I2C1_EV_IRQn
236  },
237  {
238  .dev = I2C2,
239  .speed = I2C_SPEED_NORMAL,
240  .scl_pin = GPIO_PIN(PORT_B, 10),
241  .sda_pin = GPIO_PIN(PORT_B, 11),
242  .scl_af = GPIO_AF4,
243  .sda_af = GPIO_AF4,
244  .bus = APB1,
245  .rcc_mask = RCC_APB1ENR_I2C2EN,
246  .clk = CLOCK_APB1,
247  .irqn = I2C2_EV_IRQn
248  }
249 };
250 
251 #define I2C_0_ISR isr_i2c1_ev
252 #define I2C_1_ISR isr_i2c2_ev
253 
254 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
255 
261 #define ADC_CONFIG { \
262  { GPIO_PIN(PORT_A, 0), 0 }, \
263  { GPIO_PIN(PORT_A, 1), 1 }, \
264  { GPIO_PIN(PORT_A, 4), 4 }, \
265  { GPIO_PIN(PORT_B, 0), 8 }, \
266  { GPIO_PIN(PORT_C, 1), 11 }, \
267  { GPIO_PIN(PORT_C, 0), 10 }, \
268 }
269 
270 #define ADC_NUMOF (6U)
271 
277 static const dac_conf_t dac_config[] = {
278  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
279  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
280 };
281 
282 #define DAC_NUMOF ARRAY_SIZE(dac_config)
283 
286 #ifdef __cplusplus
287 }
288 #endif
289 
290 #endif /* PERIPH_CONF_H */
291 
port C
Definition: periph_cpu.h:38
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
I2C configuration options.
Definition: periph_cpu.h:128
gpio_t pin
pin connected to the line
APB1 bus.
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:435
mini_timer_t * dev
Timer used.
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
PWM device configuration.
use alternate function 1
use alternate function 5
use alternate function 2
port A
Definition: periph_cpu.h:36
use alternate function 4
APB2 bus.
UART device configuration.
Definition: periph_cpu.h:166
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
Definition: periph_conf.h:161
DAC line configuration data.
SPI configuration structure type.
Definition: periph_cpu.h:273
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100 kbit/s
Definition: i2c.h:183
Common configuration for STM32 Timer peripheral based on TIM5.
use alternate function 7
port B
Definition: periph_cpu.h:37