periph_conf.h File Reference

Peripheral MCU configuration for the nucleo-l152re board. More...

Detailed Description

Peripheral MCU configuration for the nucleo-l152re board.

Author
Thomas Eichinger thoma.nosp@m.s.ei.nosp@m.ching.nosp@m.er@f.nosp@m.u-ber.nosp@m.lin..nosp@m.de
Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de

Definition in file periph_conf.h.

#include "periph_cpu.h"
#include "cfg_timer_tim5.h"
+ Include dependency graph for periph_conf.h:

Go to the source code of this file.

Clock system configuration

#define CLOCK_HSI   (16000000U) /* frequency of internal oscillator */
 
#define CLOCK_CORECLOCK   (32000000U) /* targeted core clock frequency */
 
#define CLOCK_LSE   (0)
 
#define CLOCK_PLL_DIV   RCC_CFGR_PLLDIV2
 
#define CLOCK_PLL_MUL   RCC_CFGR_PLLMUL4
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
 
#define CLOCK_FLASH_LATENCY   FLASH_ACR_LATENCY
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 1)
 

UART configuration

#define UART_0_ISR   (isr_usart2)
 
#define UART_1_ISR   (isr_usart1)
 
#define UART_2_ISR   (isr_usart3)
 
#define UART_NUMOF   ARRAY_SIZE(uart_config)
 
static const uart_conf_t uart_config []
 

PWM configuration

#define PWM_NUMOF   ARRAY_SIZE(pwm_config)
 
static const pwm_conf_t pwm_config []
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
#define SPI_NUMOF   ARRAY_SIZE(spi_config)
 
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 

I2C configuration

#define I2C_0_ISR   isr_i2c1_ev
 
#define I2C_1_ISR   isr_i2c2_ev
 
#define I2C_NUMOF   ARRAY_SIZE(i2c_config)
 
static const i2c_conf_t i2c_config []
 

ADC configuration

#define ADC_CONFIG
 
#define ADC_NUMOF   (6U)
 

DAC configuration

#define DAC_NUMOF   ARRAY_SIZE(dac_config)
 
static const dac_conf_t dac_config []
 

Macro Definition Documentation

◆ ADC_CONFIG

#define ADC_CONFIG
Value:
{ \
{ GPIO_PIN(PORT_A, 0), 0 }, \
{ GPIO_PIN(PORT_A, 1), 1 }, \
{ GPIO_PIN(PORT_A, 4), 4 }, \
{ GPIO_PIN(PORT_B, 0), 8 }, \
{ GPIO_PIN(PORT_C, 1), 11 }, \
{ GPIO_PIN(PORT_C, 0), 10 }, \
}
port C
Definition: periph_cpu.h:38
port A
Definition: periph_cpu.h:36
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
port B
Definition: periph_cpu.h:37

Definition at line 258 of file periph_conf.h.

Variable Documentation

◆ dac_config

const dac_conf_t dac_config[]
static
Initial value:
= {
{ .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
{ .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
}
port A
Definition: periph_cpu.h:36
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35

Definition at line 274 of file periph_conf.h.

◆ i2c_config

const i2c_conf_t i2c_config[]
static
Initial value:
= {
{
.dev = I2C1,
.speed = I2C_SPEED_NORMAL,
.scl_pin = GPIO_PIN(PORT_B, 8),
.sda_pin = GPIO_PIN(PORT_B, 9),
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
.bus = APB1,
.rcc_mask = RCC_APB1ENR_I2C1EN,
.clk = CLOCK_APB1,
.irqn = I2C1_EV_IRQn
},
{
.dev = I2C2,
.speed = I2C_SPEED_NORMAL,
.scl_pin = GPIO_PIN(PORT_B, 10),
.sda_pin = GPIO_PIN(PORT_B, 11),
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
.bus = APB1,
.rcc_mask = RCC_APB1ENR_I2C2EN,
.clk = CLOCK_APB1,
.irqn = I2C2_EV_IRQn
}
}
use alternate function 4
APB1 bus.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100kbit/s
Definition: periph_cpu.h:116
port B
Definition: periph_cpu.h:37

Definition at line 221 of file periph_conf.h.

◆ pwm_config

const pwm_conf_t pwm_config[]
static
Initial value:
= {
{
.dev = TIM2,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.chan = { { .pin = GPIO_PIN(PORT_B, 3) , .cc_chan = 1 },
{ .pin = GPIO_PIN(PORT_B, 10) , .cc_chan = 2 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
.af = GPIO_AF1,
.bus = APB1
},
{
.dev = TIM3,
.rcc_mask = RCC_APB1ENR_TIM3EN,
.chan = { { .pin = GPIO_PIN(PORT_B, 4) , .cc_chan = 0 },
{ .pin = GPIO_PIN(PORT_C, 7) , .cc_chan = 1 },
{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
.af = GPIO_AF2,
.bus = APB1
}
}
port C
Definition: periph_cpu.h:38
APB1 bus.
use alternate function 1
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
use alternate function 2
port B
Definition: periph_cpu.h:37

Definition at line 145 of file periph_conf.h.

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2,
}
}
port A
Definition: periph_cpu.h:36
APB2 bus.
use alternate function 5
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35

Definition at line 195 of file periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
5,
4,
2,
1
},
{
7,
5,
4,
2,
1
}
}

Definition at line 178 of file periph_conf.h.