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periph_conf.h
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1/*
2 * Copyright (C) 2019 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
20
21/* Add specific clock configuration (HSE, LSE) for this board here */
22#ifndef CONFIG_BOARD_HAS_LSE
23#define CONFIG_BOARD_HAS_LSE 1
24#endif
25
26#include "periph_cpu.h"
27#include "clk_conf.h"
28#include "cfg_rtt_default.h"
29#include "cfg_timer_tim2.h"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
39static const dma_conf_t dma_config[] = {
40 { .stream = 1 }, /* channel 2 */
41 { .stream = 2 }, /* channel 3 */
42 { .stream = 3 }, /* channel 4 */
43 { .stream = 4 }, /* channel 5 */
44 { .stream = 5 }, /* channel 6 */
45};
46
47#define DMA_SHARED_ISR_0 isr_dma1_channel2_3
48#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
49#define DMA_SHARED_ISR_1 isr_dma1_channel4_5_6_7
50#define DMA_SHARED_ISR_1_STREAMS { 2, 3, 4 } /* Indexes 2, 3 and 4 of dma_config share the same isr */
51
52#define DMA_NUMOF ARRAY_SIZE(dma_config)
54
59static const uart_conf_t uart_config[] = {
60 {
61 .dev = USART1,
62 .rcc_mask = RCC_APB2ENR_USART1EN,
63 .rx_pin = GPIO_PIN(PORT_A, 10),
64 .tx_pin = GPIO_PIN(PORT_A, 9),
65 .rx_af = GPIO_AF4,
66 .tx_af = GPIO_AF4,
67 .bus = APB2,
68 .irqn = USART1_IRQn,
69 .type = STM32_USART,
70 .clk_src = 0, /* Use APB clock */
71#ifdef MODULE_PERIPH_DMA
72 .dma = 0,
73 .dma_chan = 3,
74#endif
75 },
76 {
77 .dev = USART2,
78 .rcc_mask = RCC_APB1ENR_USART2EN,
79 .rx_pin = GPIO_PIN(PORT_A, 3),
80 .tx_pin = GPIO_PIN(PORT_A, 2),
81 .rx_af = GPIO_AF4,
82 .tx_af = GPIO_AF4,
83 .bus = APB1,
84 .irqn = USART2_IRQn,
85 .type = STM32_USART,
86 .clk_src = 0, /* Use APB clock */
87#ifdef MODULE_PERIPH_DMA
88 .dma = 2,
89 .dma_chan = 4,
90#endif
91 },
92};
93
94#define UART_0_ISR (isr_usart1)
95#define UART_1_ISR (isr_usart2)
96
97#define UART_NUMOF ARRAY_SIZE(uart_config)
99
104static const spi_conf_t spi_config[] = {
105 {
106 .dev = SPI1, /* connected to SX1276 */
107 .mosi_pin = GPIO_PIN(PORT_A, 7),
108 .miso_pin = GPIO_PIN(PORT_A, 6),
109 .sclk_pin = GPIO_PIN(PORT_A, 5),
110 .cs_pin = SPI_CS_UNDEF,
111 .mosi_af = GPIO_AF0,
112 .miso_af = GPIO_AF0,
113 .sclk_af = GPIO_AF0,
114 .cs_af = GPIO_AF0,
115 .rccmask = RCC_APB2ENR_SPI1EN,
116 .apbbus = APB2,
117#ifdef MODULE_PERIPH_DMA
118 .tx_dma = 1,
119 .tx_dma_chan = 1,
120 .rx_dma = 0,
121 .rx_dma_chan = 1,
122#endif
123 },
124};
125
126#define SPI_NUMOF ARRAY_SIZE(spi_config)
128
133static const i2c_conf_t i2c_config[] = {
134 {
135 .dev = I2C1,
136 .speed = I2C_SPEED_NORMAL,
137 .scl_pin = GPIO_PIN(PORT_B, 6),
138 .sda_pin = GPIO_PIN(PORT_B, 7),
139 .scl_af = GPIO_AF4,
140 .sda_af = GPIO_AF4,
141 .bus = APB1,
142 .rcc_mask = RCC_APB1ENR_I2C1EN,
143 .irqn = I2C1_IRQn
144 }
145};
146
147#define I2C_0_ISR isr_i2c1
148
149#define I2C_NUMOF ARRAY_SIZE(i2c_config)
151
152#ifdef __cplusplus
153}
154#endif
155
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:101
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
DMA configuration.
Definition cpu_dma.h:31
I2C configuration structure.
Definition periph_cpu.h:298
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217