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periph_conf.h
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1/*
2 * Copyright (C) 2021 Gerson Fernando Budke
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
18#include "mutex.h"
19
20#ifndef PERIPH_CONF_H
21#define PERIPH_CONF_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <stdint.h>
28#include <avr/io.h>
29
30#include "periph_cpu.h"
31
36static const timer_conf_t timer_config[] = {
37 {
38 .dev = (void *)&TCC1,
39 .pwr = PWR_RED_REG(PWR_PORT_C, PR_TC1_bm),
40 .type = TC_TYPE_1,
41 .int_lvl = { CPU_INT_LVL_LOW,
45 },
46 {
47 .dev = (void *)&TCC0,
48 .pwr = PWR_RED_REG(PWR_PORT_C, PR_TC0_bm),
49 .type = TC_TYPE_0,
50 .int_lvl = { CPU_INT_LVL_LOW,
54 }
55};
56
57#define TIMER_0_ISRA TCC1_CCA_vect
58
59#define TIMER_1_ISRA TCC0_CCA_vect
60#define TIMER_1_ISRB TCC0_CCB_vect
61#define TIMER_1_ISRC TCC0_CCC_vect
62#define TIMER_1_ISRD TCC0_CCD_vect
63
64#define TIMER_NUMOF ARRAY_SIZE(timer_config)
71static const uart_conf_t uart_config[] = {
72 { /* J1 */
73 .dev = &USARTF0,
74 .pwr = PWR_RED_REG(PWR_PORT_F, PR_USART0_bm),
75 .rx_pin = GPIO_PIN(PORT_F, 2),
76 .tx_pin = GPIO_PIN(PORT_F, 3),
77#ifdef MODULE_PERIPH_UART_HW_FC
78 .rts_pin = GPIO_UNDEF,
79 .cts_pin = GPIO_UNDEF,
80#endif
81 .rx_int_lvl = CPU_INT_LVL_LOW,
82 .tx_int_lvl = CPU_INT_LVL_LOW,
83 .dre_int_lvl = CPU_INT_LVL_OFF,
84 },
85 { /* J3 - Shared with SAUL */
86 .dev = &USARTD0,
87 .pwr = PWR_RED_REG(PWR_PORT_D, PR_USART0_bm),
88 .rx_pin = GPIO_PIN(PORT_D, 2),
89 .tx_pin = GPIO_PIN(PORT_D, 3),
90#ifdef MODULE_PERIPH_UART_HW_FC
91 .rts_pin = GPIO_UNDEF,
92 .cts_pin = GPIO_UNDEF,
93#endif
94 .rx_int_lvl = CPU_INT_LVL_LOW,
95 .tx_int_lvl = CPU_INT_LVL_LOW,
96 .dre_int_lvl = CPU_INT_LVL_OFF,
97 },
98 { /* J4 */
99 .dev = &USARTC0,
100 .pwr = PWR_RED_REG(PWR_PORT_C, PR_USART0_bm),
101 .rx_pin = GPIO_PIN(PORT_C, 2),
102 .tx_pin = GPIO_PIN(PORT_C, 3),
103#ifdef MODULE_PERIPH_UART_HW_FC
104 .rts_pin = GPIO_UNDEF,
105 .cts_pin = GPIO_UNDEF,
106#endif
107 .rx_int_lvl = CPU_INT_LVL_LOW,
108 .tx_int_lvl = CPU_INT_LVL_LOW,
109 .dre_int_lvl = CPU_INT_LVL_OFF,
110 },
111};
112
113/* interrupt function name mapping */
114#define UART_0_RXC_ISR USARTF0_RXC_vect /* Reception Complete Interrupt */
115#define UART_0_DRE_ISR USARTF0_DRE_vect /* Data Register Empty Interrupt */
116#define UART_0_TXC_ISR USARTF0_TXC_vect /* Transmission Complete Interrupt */
117
118#define UART_1_RXC_ISR USARTD0_RXC_vect
119#define UART_1_DRE_ISR USARTD0_DRE_vect
120#define UART_1_TXC_ISR USARTD0_TXC_vect
121
122#define UART_2_RXC_ISR USARTC0_RXC_vect
123#define UART_2_DRE_ISR USARTC0_DRE_vect
124#define UART_2_TXC_ISR USARTC0_TXC_vect
125
126#define UART_NUMOF ARRAY_SIZE(uart_config)
133static const i2c_conf_t i2c_config[] = {
134 {
135 .dev = &TWIF,
136 .pwr = PWR_RED_REG(PWR_PORT_F, PR_TWI_bm),
137 .sda_pin = GPIO_PIN(PORT_F, 0),
138 .scl_pin = GPIO_PIN(PORT_F, 1),
139 .speed = I2C_SPEED_NORMAL,
140 .int_lvl = CPU_INT_LVL_LOW,
141 },
142 {
143 .dev = &TWIC,
144 .pwr = PWR_RED_REG(PWR_PORT_C, PR_TWI_bm),
145 .sda_pin = GPIO_PIN(PORT_C, 0),
146 .scl_pin = GPIO_PIN(PORT_C, 1),
147 .speed = I2C_SPEED_NORMAL,
148 .int_lvl = CPU_INT_LVL_LOW,
149 },
150};
151
152#define I2C_0_ISR TWIF_TWIM_vect
153#define I2C_1_ISR TWIC_TWIM_vect
154
155#define I2C_NUMOF ARRAY_SIZE(i2c_config)
162static const spi_conf_t spi_config[] = {
163 {
164 .dev = &SPIF,
165 .pwr = PWR_RED_REG(PWR_PORT_F, PR_SPI_bm),
166 .sck_pin = GPIO_PIN(PORT_F, 7),
167 .miso_pin = GPIO_PIN(PORT_F, 6),
168 .mosi_pin = GPIO_PIN(PORT_F, 5),
169 .ss_pin = GPIO_PIN(PORT_F, 4),
170 },
171 {
172 .dev = &SPIC,
173 .pwr = PWR_RED_REG(PWR_PORT_C, PR_SPI_bm),
174 .sck_pin = GPIO_PIN(PORT_C, 7),
175 .miso_pin = GPIO_PIN(PORT_C, 6),
176 .mosi_pin = GPIO_PIN(PORT_C, 5),
177 .ss_pin = GPIO_PIN(PORT_C, 4),
178 },
179};
180
181#define SPI_NUMOF ARRAY_SIZE(spi_config)
191static const ebi_conf_t ebi_config = {
192 .addr_bits = 12,
193 .flags = (EBI_PORT_SDRAM | EBI_PORT_3PORT),
194 .sram_ale = 0,
195 .lpc_ale = 0,
196 .sdram = {
197 0,
198 1024,
199 6400,
200 EBI_CS_SDMODE_NORMAL_gc,
201 EBI_SDRAM_CAS_LAT_3CLK,
202 EBI_SDRAM_ROW_BITS_12,
203 EBI_SDCOL_10BIT_gc,
204 EBI_MRDLY_2CLK_gc,
205 EBI_ROWCYCDLY_7CLK_gc,
206 EBI_RPDLY_7CLK_gc,
207 EBI_WRDLY_1CLK_gc,
208 EBI_ESRDLY_7CLK_gc,
209 EBI_ROWCOLDLY_7CLK_gc,
210 },
211 .cs = { { EBI_CS_MODE_DISABLED_gc,
212 0,
213 EBI_CS_SRWS_0CLK_gc,
214 0x0UL,
215 },
216 { EBI_CS_MODE_DISABLED_gc,
217 0,
218 EBI_CS_SRWS_0CLK_gc,
219 0x0UL,
220 },
221 { EBI_CS_MODE_DISABLED_gc,
222 0,
223 EBI_CS_SRWS_0CLK_gc,
224 0x0UL,
225 },
226 { EBI_CS_MODE_SDRAM_gc,
227 EBI_CS_ASIZE_8MB_gc,
228 EBI_CS_SRWS_0CLK_gc,
229 0x0UL,
230 },
231 },
232};
235#ifdef __cplusplus
236}
237#endif
238
239#include "periph_conf_common.h"
240
241#endif /* PERIPH_CONF_H */
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_F
port F
Definition periph_cpu.h:52
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
#define PWR_RED_REG(reg, dev)
Define a CPU specific Power Reduction index macro.
Definition periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ CPU_INT_LVL_OFF
Interrupt Disabled
Definition periph_cpu.h:40
@ CPU_INT_LVL_LOW
Interrupt Low Level
Definition periph_cpu.h:41
Mutex for thread synchronization.
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219