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periph_conf.h
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1/*
2 * Copyright (C) 2024 ML!PA Consulting GmbH
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22#include "periph_cpu.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
32#ifndef CLOCK_CORECLOCK
33#define CLOCK_CORECLOCK MHZ(120)
34#endif
41#define EXTERNAL_OSC32_SOURCE 1
42#define INTERNAL_OSC32_SOURCE 0
43#define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 0
50#define USE_VREG_BUCK (1)
51
56#define ADC_GCLK_SRC SAM0_GCLK_PERIPH
57#define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
58#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
59#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
60
61static const adc_conf_chan_t adc_channels[] = {
62 /* port, pin, muxpos, dev */
63 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA02, .dev = ADC0 }, /* A0 */
64 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 }, /* A1 */
65 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA06, .dev = ADC0 }, /* A2 */
66 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 }, /* A3 */
67 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB08, .dev = ADC1 }, /* A4 */
68 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB09, .dev = ADC1 }, /* A5 */
69};
70
71#define ADC_NUMOF ARRAY_SIZE(adc_channels)
78 /* Must not exceed 12 MHz */
79#define DAC_CLOCK SAM0_GCLK_TIMER
80 /* Use external reference voltage on PA03 */
81 /* (A solder jumper connects PA03 to 3V3 on the
82 * back of the board. We assume the jumper has
83 * not been cut.) */
84#define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
91static const i2c_conf_t i2c_config[] = {
92 {
93 .dev = &(SERCOM5->I2CM),
94 .speed = I2C_SPEED_NORMAL,
95 .scl_pin = GPIO_PIN(PB, 3), /* D: SERCOM5.1 */
96 .sda_pin = GPIO_PIN(PB, 2), /* D: SERCOM5.0 */
97 .mux = GPIO_MUX_D,
98 .gclk_src = SAM0_GCLK_PERIPH,
99 .flags = I2C_FLAG_NONE
100 },
101};
102
103#define I2C_NUMOF ARRAY_SIZE(i2c_config)
110#ifndef RTT_FREQUENCY
111#define RTT_FREQUENCY (32768U)
112#endif
119static const tc32_conf_t timer_config[] = {
120 { /* Timer 0 - System Clock */
121 .dev = TC0,
122 .irq = TC0_IRQn,
123 .mclk = &MCLK->APBAMASK.reg,
124 .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
125 .gclk_id = TC0_GCLK_ID,
126 .gclk_src = SAM0_GCLK_TIMER,
127 .flags = TC_CTRLA_MODE_COUNT32,
128 },
129 { /* Timer 1 */
130 .dev = TC2,
131 .irq = TC2_IRQn,
132 .mclk = &MCLK->APBBMASK.reg,
133 .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
134 .gclk_id = TC2_GCLK_ID,
135 .gclk_src = SAM0_GCLK_TIMER,
136 .flags = TC_CTRLA_MODE_COUNT32,
137 }
138};
139
140/* Timer 0 configuration */
141#define TIMER_0_CHANNELS 2
142#define TIMER_0_ISR isr_tc0
143
144/* Timer 1 configuration */
145#define TIMER_1_CHANNELS 2
146#define TIMER_1_ISR isr_tc2
147
148#define TIMER_NUMOF ARRAY_SIZE(timer_config)
155static const spi_conf_t spi_config[] = {
156 { /* SPI on ISP */
157 .dev = &(SERCOM2->SPI),
158 .miso_pin = GPIO_PIN(PA, 14), /* C: SERCOM2.2, D: SERCOM4.2 */
159 .mosi_pin = GPIO_PIN(PA, 12), /* C: SERCOM2.0, D: SERCOM4.1 */
160 .clk_pin = GPIO_PIN(PA, 13), /* C: SERCOM2.1, D: SERCOM4.0 */
161 .miso_mux = GPIO_MUX_C,
162 .mosi_mux = GPIO_MUX_C,
163 .clk_mux = GPIO_MUX_C,
164 .miso_pad = SPI_PAD_MISO_2,
165 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
166 .gclk_src = SAM0_GCLK_PERIPH,
167#if MODULE_PERIPH_DMA
168 .tx_trigger = SERCOM2_DMAC_ID_TX,
169 .rx_trigger = SERCOM2_DMAC_ID_RX,
170#endif
171 },
172#if !MODULE_PERIPH_UART
173 { /* D11=MOSI, D12=MISO, D13=SCK */
174 .dev = &(SERCOM3->SPI),
175 .miso_pin = GPIO_PIN(PA, 17), /* C: SERCOM1.1, D: SERCOM3.0 */
176 .mosi_pin = GPIO_PIN(PA, 19), /* C: SERCOM1.3, D: SERCOM3.3 */
177 .clk_pin = GPIO_PIN(PA, 16), /* C: SERCOM1.0, D: SERCOM3.1 */
178 .miso_mux = GPIO_MUX_D,
179 .mosi_mux = GPIO_MUX_D,
180 .clk_mux = GPIO_MUX_D,
181 .miso_pad = SPI_PAD_MISO_0,
182 .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
183 .gclk_src = SAM0_GCLK_PERIPH,
184# if MODULE_PERIPH_DMA
185 .tx_trigger = SERCOM3_DMAC_ID_TX,
186 .rx_trigger = SERCOM3_DMAC_ID_RX,
187# endif
188 },
189#endif
190#if MODULE_PERIPH_SPI_ON_QSPI
191 { /* QSPI in SPI mode */
192 .dev = QSPI,
193 .miso_pin = SAM0_QSPI_PIN_DATA_1,
194 .mosi_pin = SAM0_QSPI_PIN_DATA_0,
195 .clk_pin = SAM0_QSPI_PIN_CLK,
196 .miso_mux = SAM0_QSPI_MUX,
197 .mosi_mux = SAM0_QSPI_MUX,
198 .clk_mux = SAM0_QSPI_MUX,
199 .miso_pad = SPI_PAD_MISO_0, /* unused */
200 .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
201 .gclk_src = SAM0_GCLK_MAIN, /* unused */
202# if MODULE_PERIPH_DMA
203 .tx_trigger = QSPI_DMAC_ID_TX,
204 .rx_trigger = QSPI_DMAC_ID_RX,
205# endif
206 },
207#endif
208};
209
210#define SPI_NUMOF ARRAY_SIZE(spi_config)
217static const sam0_common_usb_config_t sam_usbdev_config[] = {
218 {
219 .dm = GPIO_PIN(PA, 24),
220 .dp = GPIO_PIN(PA, 25),
221 .d_mux = GPIO_MUX_H,
222 .device = &USB->DEVICE,
223 .gclk_src = SAM0_GCLK_PERIPH,
224 }
225};
232static const uart_conf_t uart_config[] = {
233/* The UART pins can be routed to SERCOM3 (used by SPI) or
234 * SERCOM5 (used by I2C). The pad configuration for SERCOM5
235 * is impossible, as TXD cannot be routed to pad 1.
236 * Hence, we let periph_spi and periph_uart conflict in
237 * Makefile.features.
238 */
239 /* D0 = RXD, D1 = TXD */
240 {
241 .dev = &SERCOM3->USART,
242 .rx_pin = GPIO_PIN(PA, 23), /* C: SERCOM3.1, D: SERCOM5.0 */
243 .tx_pin = GPIO_PIN(PA, 22), /* C: SERCOM3.0, D: SERCOM5.1 */
244 #ifdef MODULE_PERIPH_UART_HW_FC
245 .rts_pin = GPIO_UNDEF,
246 .cts_pin = GPIO_UNDEF,
247 #endif
248 .mux = GPIO_MUX_C,
249 .rx_pad = UART_PAD_RX_1,
250 .tx_pad = UART_PAD_TX_0,
251 .flags = UART_FLAG_NONE,
252 .gclk_src = SAM0_GCLK_PERIPH,
253 },
254};
255
256/* interrupt function name mapping */
257#define UART_0_ISR isr_sercom3_2
258#define UART_0_ISR_TX isr_sercom3_0
259
260#define UART_NUMOF ARRAY_SIZE(uart_config)
263#ifdef __cplusplus
264}
265#endif
266
267#endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define ADC1_INPUTCTRL_MUXPOS_PB09
Alias for AIN1.
Definition periph_cpu.h:144
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:74
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition periph_cpu.h:130
#define ADC1_INPUTCTRL_MUXPOS_PB08
Alias for AIN0.
Definition periph_cpu.h:143
#define SAM0_QSPI_PIN_CLK
Clock
Definition periph_cpu.h:269
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition periph_cpu.h:131
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI
Definition periph_cpu.h:271
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO
Definition periph_cpu.h:272
#define SAM0_QSPI_MUX
QSPI mux
Definition periph_cpu.h:275
#define ADC0_INPUTCTRL_MUXPOS_PA06
Alias for AIN6.
Definition periph_cpu.h:132
#define SAM0_GCLK_TIMER
4-8 MHz clock for xTimer
Definition periph_cpu.h:79
#define ADC0_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:126
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition periph_cpu.h:82
ADC Channel Configuration.
uint32_t inputctrl
ADC channel pin multiplexer value
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Tc * dev
pointer to the used Timer device
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219