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periph_conf.h
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1/*
2 * Copyright (C) 2014-2016 Freie Universität Berlin
3 * 2018 HAW Hamburg
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
24#ifndef PERIPH_CONF_H
25#define PERIPH_CONF_H
26
27/*
28 * This board provides an LSE, so enable it before including the default clock config
29 */
30#ifndef CONFIG_BOARD_HAS_LSE
31#define CONFIG_BOARD_HAS_LSE 1
32#endif
33
34#include "periph_cpu.h"
35#include "clk_conf.h"
36#include "cfg_timer_tim2.h"
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
46static const uart_conf_t uart_config[] = {
47 {
48 .dev = USART1,
49 .rcc_mask = RCC_APB2ENR_USART1EN,
50 .rx_pin = GPIO_PIN(PORT_A, 10),
51 .tx_pin = GPIO_PIN(PORT_A, 9),
52 .rx_af = GPIO_AF7,
53 .tx_af = GPIO_AF7,
54 .bus = APB2,
55 .irqn = USART1_IRQn
56 },
57 {
58 .dev = USART2,
59 .rcc_mask = RCC_APB1ENR_USART2EN,
60 .rx_pin = GPIO_PIN(PORT_A, 3),
61 .tx_pin = GPIO_PIN(PORT_A, 2),
62 .rx_af = GPIO_AF7,
63 .tx_af = GPIO_AF7,
64 .bus = APB1,
65 .irqn = USART2_IRQn
66 }
67};
68
69#define UART_0_ISR (isr_usart1)
70#define UART_1_ISR (isr_usart2)
71
72#define UART_NUMOF ARRAY_SIZE(uart_config)
79#define PWM_NUMOF 0
86static const spi_conf_t spi_config[] = {
87 {
88 .dev = SPI1,
89 .mosi_pin = GPIO_PIN(PORT_A, 7),
90 .miso_pin = GPIO_PIN(PORT_A, 6),
91 .sclk_pin = GPIO_PIN(PORT_A, 5),
92 .cs_pin = GPIO_PIN(PORT_B, 0),
93 .mosi_af = GPIO_AF5,
94 .miso_af = GPIO_AF5,
95 .sclk_af = GPIO_AF5,
96 .cs_af = GPIO_AF5,
97 .rccmask = RCC_APB2ENR_SPI1EN,
98 .apbbus = APB2
99 },
100 {
101 .dev = SPI2,
102 .mosi_pin = GPIO_PIN(PORT_B, 14),
103 .miso_pin = GPIO_PIN(PORT_B, 15),
104 .sclk_pin = GPIO_PIN(PORT_B, 13),
105 .cs_pin = GPIO_PIN(PORT_B, 12),
106 .mosi_af = GPIO_AF5,
107 .miso_af = GPIO_AF5,
108 .sclk_af = GPIO_AF5,
109 .cs_af = GPIO_AF5,
110 .rccmask = RCC_APB1ENR_SPI2EN,
111 .apbbus = APB1
112 }
113};
114
115#define SPI_NUMOF ARRAY_SIZE(spi_config)
122static const i2c_conf_t i2c_config[] = {
123 {
124 .dev = I2C1,
125 .speed = I2C_SPEED_NORMAL,
126 .scl_pin = GPIO_PIN(PORT_B, 8),
127 .sda_pin = GPIO_PIN(PORT_B, 9),
128 .scl_af = GPIO_AF4,
129 .sda_af = GPIO_AF4,
130 .bus = APB1,
131 .rcc_mask = RCC_APB1ENR_I2C1EN,
132 .clk = CLOCK_APB1,
133 .irqn = I2C1_EV_IRQn
134 }
135};
136
137#define I2C_0_ISR isr_i2c1_ev
138
139#define I2C_NUMOF ARRAY_SIZE(i2c_config)
142#ifdef __cplusplus
143}
144#endif
145
146#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219