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periph_conf.h
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1/*
2 * Copyright (C) 2019 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* Add specific clock configuration (HSE, LSE) for this board here */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27#include "periph_cpu.h"
28#include "clk_conf.h"
29#include "cfg_rtt_default.h"
30#include "cfg_timer_tim2.h"
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
40static const uart_conf_t uart_config[] = {
41 {
42 .dev = LPUART1,
43 .rcc_mask = RCC_APB1ENR_LPUART1EN,
44 .rx_pin = GPIO_PIN(PORT_B, 11),
45 .tx_pin = GPIO_PIN(PORT_B, 10),
46 .rx_af = GPIO_AF4,
47 .tx_af = GPIO_AF4,
48 .bus = APB1,
49 .irqn = LPUART1_IRQn,
50 .type = STM32_LPUART,
51 .clk_src = 0, /* Use APB clock */
52 },
53};
54
55#define UART_0_ISR (isr_rng_lpuart1)
56
57#define UART_NUMOF ARRAY_SIZE(uart_config)
64static const spi_conf_t spi_config[] = {
65 {
66 .dev = SPI1, /* connected to SX1272 */
67 .mosi_pin = GPIO_PIN(PORT_A, 12),
68 .miso_pin = GPIO_PIN(PORT_B, 4),
69 .sclk_pin = GPIO_PIN(PORT_B, 3),
70 .cs_pin = GPIO_PIN(PORT_A, 15),
71 .mosi_af = GPIO_AF0,
72 .miso_af = GPIO_AF0,
73 .sclk_af = GPIO_AF0,
74 .cs_af = GPIO_AF0,
75 .rccmask = RCC_APB2ENR_SPI1EN,
76 .apbbus = APB2,
77 },
78};
79
80#define SPI_NUMOF ARRAY_SIZE(spi_config)
87static const i2c_conf_t i2c_config[] = {
88 {
89 .dev = I2C1,
90 .speed = I2C_SPEED_NORMAL,
91 .scl_pin = GPIO_PIN(PORT_B, 6),
92 .sda_pin = GPIO_PIN(PORT_B, 7),
93 .scl_af = GPIO_AF1,
94 .sda_af = GPIO_AF1,
95 .bus = APB1,
96 .rcc_mask = RCC_APB1ENR_I2C1EN,
97 .irqn = I2C1_IRQn
98 }
99};
100
101#define I2C_0_ISR isr_i2c1
102
103#define I2C_NUMOF ARRAY_SIZE(i2c_config)
106#ifdef __cplusplus
107}
108#endif
109
110#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:102
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:39
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219