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periph_conf.h
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1/*
2 * Copyright (C) 2021 Luo Jia (HUST IoT Security Lab)
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
9#pragma once
10
20
21/* Add specific clock configuration (HSE, LSE) for this board here */
22#ifndef CONFIG_BOARD_HAS_LSE
23#define CONFIG_BOARD_HAS_LSE 1
24#endif
25
26#include "periph_cpu.h"
27#include "clk_conf.h"
28#include "cfg_rtt_default.h"
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
39static const timer_conf_t timer_config[] = {
40 {
41 .dev = TIM5,
42 .max = 0xffffffff,
43 .rcc_mask = RCC_APB1ENR1_TIM5EN,
44 .bus = APB1,
45 .irqn = TIM5_IRQn
46 }
47};
48
49#define TIMER_0_ISR isr_tim5
50
51#define TIMER_NUMOF ARRAY_SIZE(timer_config)
53
59static const uart_conf_t uart_config[] = {
60 {
61 .dev = USART1,
62 .rcc_mask = RCC_APB2ENR_USART1EN,
63 .rx_pin = GPIO_PIN(PORT_A, 10),
64 .tx_pin = GPIO_PIN(PORT_A, 9),
65 .rx_af = GPIO_AF7,
66 .tx_af = GPIO_AF7,
67 .bus = APB2,
68 .irqn = USART1_IRQn,
69 .type = STM32_USART,
70 .clk_src = 0, /* Use APB clock */
71#ifdef UART_USE_DMA
72 .dma_stream = 6,
73 .dma_chan = 4
74#endif
75 }
76};
77
78#define UART_0_ISR (isr_usart1)
79
80#define UART_NUMOF ARRAY_SIZE(uart_config)
82
83#ifdef __cplusplus
84}
85#endif
86
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
Timer device configuration.
Definition periph_cpu.h:263
UART device configuration.
Definition periph_cpu.h:217