sam3/include/periph_cpu.h File Reference

CPU specific definitions for internal peripheral handling. More...

Detailed Description

CPU specific definitions for internal peripheral handling.

Author
Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de
Tobias Fredersdorf tobia.nosp@m.s.fr.nosp@m.eders.nosp@m.dorf.nosp@m.@haw-.nosp@m.hamb.nosp@m.urg.d.nosp@m.e

Definition in file sam3/include/periph_cpu.h.

#include "cpu.h"
+ Include dependency graph for sam3/include/periph_cpu.h:

Go to the source code of this file.

Data Structures

struct  timer_conf_t
 Timer configuration. More...
 
struct  uart_conf_t
 UART device configuration. More...
 
struct  pwm_chan_conf_t
 PWM channel configuration data. More...
 
struct  spi_conf_t
 SPI module configuration options. More...
 

Macros

#define GPIO_UNDEF   (0xffffffff)
 Definition of a fitting UNDEF value.
 
#define GPIO_PIN(x, y)   (((uint32_t)PIOA + (x << 9)) | y)
 Define a CPU specific GPIO pin generator macro.
 
#define CPUID_LEN   (16U)
 Length of the CPU_ID in octets.
 
#define TIMER_MAX_VAL   (0xffffffff)
 All SAM3 timers are 32-bit wide.
 
#define TIMER_CHANNELS   (3)
 We use 3 channels for each defined timer.
 
#define GPIO_MODE(io, pu, od)   (io | (pu << 1) | (od << 2))
 Generate GPIO mode bitfields. More...
 
#define PERIPH_SPI_NEEDS_INIT_CS
 Declare needed generic SPI functions.
 
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
 
#define PERIPH_SPI_NEEDS_TRANSFER_REG
 
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 

Functions

void gpio_init_mux (gpio_t pin, gpio_mux_t mux)
 Configure the given GPIO pin to be used with the given MUX setting. More...
 
#define HAVE_GPIO_T
 Overwrite the default gpio_t type definition.
 
typedef uint32_t gpio_t
 

ADC configuration, valid for all boards using this CPU

The sam3 has a fixed mapping of ADC pins and a fixed number of ADC channels, so this ADC configuration is valid for all boards using this CPU.

No need for any board specific configuration.

#define ADC_NUMOF   (16U)
 
#define DAC_NUMOF   (2U)
 DAC configuration, valid for all boards using this CPU. More...
 
#define HAVE_SPI_MODE_T
 Override default SPI modes.
 
enum  { PA = 0, PB = 1, PC = 2, PD = 3 }
 Available ports on the SAM3X8E. More...
 
enum  gpio_mux_t {
  GPIO_MUX_A = 0x0, GPIO_MUX_B = 0x1, GPIO_MUX_C = 0x2, GPIO_MUX_D = 0x3,
  GPIO_MUX_E = 0x4, GPIO_MUX_F = 0x5, GPIO_MUX_G = 0x6, GPIO_MUX_H = 0x7,
  GPIO_MUX_A = 0, GPIO_MUX_B = 1
}
 GPIO mux configuration. More...
 
enum  spi_mode_t {
  SPI_MODE_0 = SPI_MODE_SEL(0, 0), SPI_MODE_1 = SPI_MODE_SEL(0, 1), SPI_MODE_2 = SPI_MODE_SEL(1, 0), SPI_MODE_3 = SPI_MODE_SEL(1, 1),
  SPI_MODE_0 = 0, SPI_MODE_1 = (SSI_CR0_SPH), SPI_MODE_2 = (SSI_CR0_SPO), SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH),
  SPI_MODE_0 = SSI_FRF_MOTO_MODE_0, SPI_MODE_1 = SSI_FRF_MOTO_MODE_1, SPI_MODE_2 = SSI_FRF_MOTO_MODE_2, SPI_MODE_3 = SSI_FRF_MOTO_MODE_0,
  SPI_MODE_0 = 0, SPI_MODE_1 = SPI_CONFIG_CPHA_Msk, SPI_MODE_2 = SPI_CONFIG_CPOL_Msk, SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk),
  SPI_MODE_0 = 0x0, SPI_MODE_1 = 0x1, SPI_MODE_2 = 0x2, SPI_MODE_3 = 0x3,
  SPI_MODE_0 = (SPI_CSR_NCPHA), SPI_MODE_1 = (0), SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA), SPI_MODE_3 = (SPI_CSR_CPOL),
  SPI_MODE_0 = 0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3
}
 
#define HAVE_SPI_CLK_T
 Override default SPI clock values.
 
enum  spi_clk_t {
  SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1), SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0), SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1), SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0),
  SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0), SPI_CLK_100KHZ = 0, SPI_CLK_400KHZ = 1, SPI_CLK_1MHZ = 2,
  SPI_CLK_5MHZ = 3, SPI_CLK_10MHZ = 4, SPI_CLK_100KHZ = 100000, SPI_CLK_400KHZ = 400000,
  SPI_CLK_1MHZ = 1000000, SPI_CLK_4MHZ = 4000000, SPI_CLK_5MHZ = 5000000, SPI_CLK_10MHZ = 10000000,
  SPI_CLK_100KHZ = 100, SPI_CLK_400KHZ = 400, SPI_CLK_1MHZ = 1000, SPI_CLK_5MHZ = 5000,
  SPI_CLK_10MHZ = 10000, SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125, SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500, SPI_CLK_1MHZ = SPI_FREQUENCY_FREQUENCY_M1,
  SPI_CLK_5MHZ = SPI_FREQUENCY_FREQUENCY_M4, SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8, SPI_CLK_100KHZ = 100000U, SPI_CLK_400KHZ = 400000U,
  SPI_CLK_1MHZ = 1000000U, SPI_CLK_5MHZ = 5000000U, SPI_CLK_10MHZ = 10000000U, SPI_CLK_100KHZ = (100000),
  SPI_CLK_400KHZ = (400000), SPI_CLK_1MHZ = (1000000), SPI_CLK_5MHZ = (5000000), SPI_CLK_10MHZ = (10000000),
  SPI_CLK_100KHZ = 0, SPI_CLK_400KHZ, SPI_CLK_1MHZ, SPI_CLK_5MHZ,
  SPI_CLK_10MHZ
}
 
#define HAVE_ADC_RES_T
 Override ADC resolution values.
 
enum  adc_res_t {
  ADC_RES_6BIT = (0xa00), ADC_RES_7BIT = (0 << 4), ADC_RES_8BIT = (0xb00), ADC_RES_9BIT = (1 << 4),
  ADC_RES_10BIT = (2 << 4), ADC_RES_12BIT = (3 << 4), ADC_RES_14BIT = (0xc00), ADC_RES_16BIT = (0xd00),
  ADC_RES_6BIT = 0x1, ADC_RES_8BIT = 0x2, ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10, ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
  ADC_RES_14BIT = 0x4, ADC_RES_16BIT = 0x8, ADC_RES_6BIT = 0xff, ADC_RES_8BIT = ADC_CTRLB_RESSEL_8BIT,
  ADC_RES_10BIT = ADC_CTRLB_RESSEL_10BIT, ADC_RES_12BIT = ADC_CTRLB_RESSEL_12BIT, ADC_RES_14BIT = 0xfe, ADC_RES_16BIT = 0xfd,
  ADC_RES_6BIT = 0xff, ADC_RES_8BIT = ADC_CTRLC_RESSEL_8BIT, ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT, ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT,
  ADC_RES_14BIT = 0xfe, ADC_RES_16BIT = 0xfd, ADC_RES_6BIT = 0x03000000, ADC_RES_8BIT = 0x02000000,
  ADC_RES_10BIT = 0x01000000, ADC_RES_12BIT = 0x00000000, ADC_RES_14BIT = 1, ADC_RES_16BIT = 2,
  ADC_RES_6BIT = (0x3 << 3), ADC_RES_8BIT = (0x2 << 3), ADC_RES_10BIT = (0x1 << 3), ADC_RES_12BIT = (0x0 << 3),
  ADC_RES_14BIT = (0xfe), ADC_RES_16BIT = (0xff), ADC_RES_6BIT = 0, ADC_RES_8BIT,
  ADC_RES_10BIT, ADC_RES_12BIT, ADC_RES_14BIT, ADC_RES_16BIT
}
 

Macro Definition Documentation

◆ DAC_NUMOF

#define DAC_NUMOF   (2U)

DAC configuration, valid for all boards using this CPU.

The sam3 has a fixed mapping of DAC pins and a fixed number of DAC channels, so this DAC configuration is valid for all boards using this CPU. No need for any board specific configuration.

The sam3's DAC channels are mapped to the following fixed pins:

  • line 0 (ch0): PB15
  • line 1 (ch1): PB16

Definition at line 103 of file sam3/include/periph_cpu.h.

◆ GPIO_MODE

#define GPIO_MODE (   io,
  pu,
  od 
)    (io | (pu << 1) | (od << 2))

Generate GPIO mode bitfields.

We use 3 bit to determine the pin functions:

  • bit 0: in/out
  • bit 1: PU enable
  • bit 2: OD enable

Definition at line 81 of file sam3/include/periph_cpu.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Available ports on the SAM3X8E.

Enumerator
PA 

port A

PB 

port B

PC 

port C

PD 

port D

Definition at line 137 of file sam3/include/periph_cpu.h.

◆ adc_res_t

enum adc_res_t
Enumerator
ADC_RES_6BIT 

not supported by hardware

ADC_RES_7BIT 

ADC resolution: 7 bit.

ADC_RES_8BIT 

not supported by hardware

ADC_RES_9BIT 

ADC resolution: 9 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not supported by hardware

ADC_RES_16BIT 

not supported by hardware

ADC_RES_6BIT 

not applicable

ADC_RES_8BIT 

not applicable

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not applicable

ADC_RES_16BIT 

not applicable

ADC_RES_6BIT 

not supported

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not supported

ADC_RES_16BIT 

not supported

ADC_RES_6BIT 

not supported

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not supported

ADC_RES_16BIT 

not supported

ADC_RES_6BIT 

ADC resolution: 6 bit.

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

ADC resolution: 14 bit (not supported)

ADC_RES_16BIT 

ADC resolution: 16 bit (not supported)

ADC_RES_6BIT 

ADC resolution: 6 bit.

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

not applicable

ADC_RES_16BIT 

not applicable

ADC_RES_6BIT 

ADC resolution: 6 bit.

ADC_RES_8BIT 

ADC resolution: 8 bit.

ADC_RES_10BIT 

ADC resolution: 10 bit.

ADC_RES_12BIT 

ADC resolution: 12 bit.

ADC_RES_14BIT 

ADC resolution: 14 bit.

ADC_RES_16BIT 

ADC resolution: 16 bit.

Definition at line 184 of file sam3/include/periph_cpu.h.

◆ gpio_mux_t

enum gpio_mux_t

GPIO mux configuration.

Enumerator
GPIO_MUX_A 

select peripheral function A

GPIO_MUX_B 

select peripheral function B

GPIO_MUX_C 

select peripheral function C

GPIO_MUX_D 

select peripheral function D

GPIO_MUX_E 

select peripheral function E

GPIO_MUX_F 

select peripheral function F

GPIO_MUX_G 

select peripheral function G

GPIO_MUX_H 

select peripheral function H

GPIO_MUX_A 

alternate function A

GPIO_MUX_B 

alternate function B

Definition at line 147 of file sam3/include/periph_cpu.h.

◆ spi_clk_t

enum spi_clk_t
Enumerator
SPI_CLK_100KHZ 

16/128 -> 125KHz

SPI_CLK_400KHZ 

16/32 -> 500KHz

SPI_CLK_1MHZ 

16/16 -> 1MHz

SPI_CLK_5MHZ 

16/4 -> 4MHz

SPI_CLK_10MHZ 

16/2 -> 8MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_4MHZ 

drive the SPI bus with 4MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

100KHz

SPI_CLK_400KHZ 

400KHz

SPI_CLK_1MHZ 

1MHz

SPI_CLK_5MHZ 

5MHz

SPI_CLK_10MHZ 

10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

SPI_CLK_100KHZ 

100KHz

SPI_CLK_400KHZ 

400KHz

SPI_CLK_1MHZ 

1MHz

SPI_CLK_5MHZ 

5MHz

SPI_CLK_10MHZ 

10MHz

SPI_CLK_100KHZ 

drive the SPI bus with 100KHz

SPI_CLK_400KHZ 

drive the SPI bus with 400KHz

SPI_CLK_1MHZ 

drive the SPI bus with 1MHz

SPI_CLK_5MHZ 

drive the SPI bus with 5MHz

SPI_CLK_10MHZ 

drive the SPI bus with 10MHz

Definition at line 170 of file sam3/include/periph_cpu.h.

◆ spi_mode_t

enum spi_mode_t
Enumerator
SPI_MODE_0 

mode 0

SPI_MODE_1 

mode 1

SPI_MODE_2 

mode 2

SPI_MODE_3 

mode 3

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

SPI_MODE_0 

CPOL=0, CPHA=0.

SPI_MODE_1 

CPOL=0, CPHA=1.

SPI_MODE_2 

CPOL=1, CPHA=0.

SPI_MODE_3 

CPOL=1, CPHA=1.

Definition at line 157 of file sam3/include/periph_cpu.h.

Function Documentation

◆ gpio_init_mux()

void gpio_init_mux ( gpio_t  pin,
gpio_mux_t  mux 
)

Configure the given GPIO pin to be used with the given MUX setting.

Parameters
[in]pinGPIO pin to configure
[in]muxMUX setting to use