periph_cpu.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
22 #ifndef PERIPH_CPU_H
23 #define PERIPH_CPU_H
24 
25 #include "cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
34 #define HAVE_GPIO_T
35 typedef uint32_t gpio_t;
41 #define GPIO_UNDEF (0xffffffff)
42 
46 #define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
47 
52 #define PERIPH_SPI_NEEDS_INIT_CS
53 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
54 #define PERIPH_SPI_NEEDS_TRANSFER_REG
55 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
56 
61 #define CPUID_LEN (16U)
62 
66 #define TIMER_MAX_VAL (0xffffffff)
67 
71 #define TIMER_CHANNELS (3)
72 
76 #define RTT_MAX_VALUE (0xffffffff)
77 
86 #define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
87 
95 #define ADC_NUMOF (16U)
96 
108 #define DAC_NUMOF (2U)
109 
110 #ifndef DOXYGEN
111 
115 #define HAVE_GPIO_MODE_T
116 typedef enum {
117  GPIO_IN = GPIO_MODE(0, 0, 0),
118  GPIO_IN_PD = 0xf,
119  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
120  GPIO_OUT = GPIO_MODE(1, 0, 0),
121  GPIO_OD = GPIO_MODE(1, 0, 1),
122  GPIO_OD_PU = GPIO_MODE(1, 1, 1),
123 } gpio_mode_t;
130 #define HAVE_GPIO_FLANK_T
131 typedef enum {
132  GPIO_RISING = 1,
133  GPIO_FALLING = 2,
134  GPIO_BOTH = 3
135 } gpio_flank_t;
137 #endif /* ndef DOXYGEN */
138 
142 enum {
143  PA = 0,
144  PB = 1,
145  PC = 2,
146  PD = 3,
147 };
148 
152 typedef enum {
155 } gpio_mux_t;
156 
157 #ifndef DOXYGEN
158 
162 #define HAVE_SPI_MODE_T
163 typedef enum {
164  SPI_MODE_0 = (SPI_CSR_NCPHA),
165  SPI_MODE_1 = (0),
166  SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA),
167  SPI_MODE_3 = (SPI_CSR_CPOL)
168 } spi_mode_t;
175 #define HAVE_SPI_CLK_T
176 typedef enum {
177  SPI_CLK_100KHZ = (100000),
178  SPI_CLK_400KHZ = (400000),
179  SPI_CLK_1MHZ = (1000000),
180  SPI_CLK_5MHZ = (5000000),
181  SPI_CLK_10MHZ = (10000000)
182 } spi_clk_t;
184 #endif /* ndef DOXYGEN */
185 
186 #ifndef DOXYGEN
187 
191 #define HAVE_ADC_RES_T
192 typedef enum {
193  ADC_RES_6BIT = 0x1,
194  ADC_RES_8BIT = 0x2,
195  ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10,
196  ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
197  ADC_RES_14BIT = 0x4,
198  ADC_RES_16BIT = 0x8
199 } adc_res_t;
201 #endif /* ndef DOXYGEN */
202 
206 typedef struct {
207  Tc *dev;
208  uint8_t id_ch0;
209 } timer_conf_t;
210 
214 typedef struct {
215  Uart *dev;
216  gpio_t rx_pin;
217  gpio_t tx_pin;
218  gpio_mux_t mux;
219  uint8_t pmc_id;
220  uint8_t irqn;
221 } uart_conf_t;
222 
226 typedef struct {
227  gpio_t pin;
228  uint8_t hwchan;
230 
234 typedef struct {
235  Spi *dev;
236  uint8_t id;
237  gpio_t clk;
238  gpio_t mosi;
239  gpio_t miso;
241 } spi_conf_t;
242 
249 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
250 
251 #ifdef __cplusplus
252 }
253 #endif
254 
255 #endif /* PERIPH_CPU_H */
256 
alternate function B
Definition: periph_cpu.h:154
CPOL=0, CPHA=1.
Definition: spi.h:159
configure as output in push-pull mode
Definition: gpio.h:117
Uart * dev
U(S)ART device used.
Definition: periph_cpu.h:215
emit interrupt on rising flank
Definition: gpio.h:131
uint8_t irqn
interrupt number of the device
Definition: periph_cpu.h:220
ADC resolution: 12 bit.
Definition: adc.h:97
PWM channel configuration.
Definition: periph_cpu.h:274
gpio_mux_t
GPIO mux configuration.
Definition: periph_cpu.h:152
Tc * dev
timer device
Definition: periph_cpu.h:207
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:93
gpio_mux_t mux
pin MUX setting
Definition: periph_cpu.h:240
port A
Definition: periph_cpu.h:87
port B
Definition: periph_cpu.h:88
CPOL=0, CPHA=0.
Definition: spi.h:158
drive the SPI bus with 100KHz
Definition: spi.h:174
port C
Definition: periph_cpu.h:89
uint8_t id_ch0
ID of the timer&#39;s first channel.
Definition: periph_cpu.h:208
drive the SPI bus with 400KHz
Definition: spi.h:175
uint8_t pmc_id
bit in the PMC register of the device
Definition: periph_cpu.h:219
uint8_t id
corresponding ID of that module
Definition: periph_cpu.h:236
emit interrupt on both flanks
Definition: gpio.h:132
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:129
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
ADC resolution: 14 bit.
Definition: adc.h:98
ADC resolution: 10 bit.
Definition: adc.h:96
spi_clk_t
Available SPI clock speeds.
Definition: spi.h:173
CPOL=1, CPHA=1.
Definition: spi.h:161
port D
Definition: periph_cpu.h:90
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
Spi * dev
SPI module to use.
Definition: periph_cpu.h:235
ADC resolution: 16 bit.
Definition: adc.h:99
gpio_mux_t
Available MUX values for configuring a pin&#39;s alternate function.
drive the SPI bus with 5MHz
Definition: spi.h:177
ADC resolution: 8 bit.
Definition: adc.h:95
alternate function A
Definition: periph_cpu.h:153
uint8_t hwchan
the HW channel used for a logical channel
Definition: periph_cpu.h:228
ADC resolution: 6 bit.
Definition: adc.h:94
drive the SPI bus with 10MHz
Definition: spi.h:178
emit interrupt on falling flank
Definition: gpio.h:130
drive the SPI bus with 1MHz
Definition: spi.h:176
configure as input with pull-up resistor
Definition: gpio.h:116
void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func)
Configure an alternate function for the given pin.
UART device configuration.
Definition: periph_cpu.h:166
gpio_mode_t
Available pin modes.
Definition: gpio.h:113
configure as input without pull resistor
Definition: gpio.h:114
gpio_t clk
pin mapped to the CLK line
Definition: periph_cpu.h:237
configure as output in open-drain mode without pull resistor
Definition: gpio.h:118
CPOL=1, CPHA=0.
Definition: spi.h:160
SPI configuration structure type.
Definition: periph_cpu.h:273
configure as input with pull-down resistor
Definition: gpio.h:115
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:120
#define GPIO_MODE(io, pu, od)
Generate GPIO mode bitfields.
Definition: periph_cpu.h:86
Timer configuration.
Definition: periph_cpu.h:288