sam3/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
22 #ifndef PERIPH_CPU_H
23 #define PERIPH_CPU_H
24 
25 #include "cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
34 #define HAVE_GPIO_T
35 typedef uint32_t gpio_t;
41 #define GPIO_UNDEF (0xffffffff)
42 
46 #define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
47 
52 #define PERIPH_SPI_NEEDS_INIT_CS
53 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
54 #define PERIPH_SPI_NEEDS_TRANSFER_REG
55 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
56 
61 #define CPUID_LEN (16U)
62 
66 #define TIMER_MAX_VAL (0xffffffff)
67 
71 #define TIMER_CHANNELS (3)
72 
81 #define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
82 
83 #ifndef DOXYGEN
84 
88 #define HAVE_GPIO_MODE_T
89 typedef enum {
90  GPIO_IN = GPIO_MODE(0, 0, 0),
91  GPIO_IN_PD = 0xf,
92  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
93  GPIO_OUT = GPIO_MODE(1, 0, 0),
94  GPIO_OD = GPIO_MODE(1, 0, 1),
95  GPIO_OD_PU = GPIO_MODE(1, 1, 1),
96 } gpio_mode_t;
103 #define HAVE_GPIO_FLANK_T
104 typedef enum {
105  GPIO_RISING = 1,
106  GPIO_FALLING = 2,
107  GPIO_BOTH = 3
108 } gpio_flank_t;
110 #endif /* ndef DOXYGEN */
111 
115 enum {
116  PA = 0,
117  PB = 1,
118  PC = 2,
119  PD = 3,
120 };
121 
125 typedef enum {
128 } gpio_mux_t;
129 
134 #define HAVE_SPI_MODE_T
135 typedef enum {
136  SPI_MODE_0 = (SPI_CSR_NCPHA),
137  SPI_MODE_1 = (0),
138  SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA),
139  SPI_MODE_3 = (SPI_CSR_CPOL)
140 } spi_mode_t;
147 #define HAVE_SPI_CLK_T
148 typedef enum {
149  SPI_CLK_100KHZ = (100000),
150  SPI_CLK_400KHZ = (400000),
151  SPI_CLK_1MHZ = (1000000),
152  SPI_CLK_5MHZ = (5000000),
153  SPI_CLK_10MHZ = (10000000)
154 } spi_clk_t;
160 typedef struct {
161  Tc *dev;
162  uint8_t id_ch0;
163 } timer_conf_t;
164 
168 typedef struct {
169  Uart *dev;
170  Pio *rx_port;
171  Pio *tx_port;
172  uint8_t rx_pin;
173  uint8_t tx_pin;
175  uint8_t pmc_id;
176  uint8_t irqn;
177 } uart_conf_t;
178 
182 typedef struct {
183  gpio_t pin;
184  uint8_t hwchan;
186 
190 typedef struct {
191  Spi *dev;
192  uint8_t id;
193  gpio_t clk;
194  gpio_t mosi;
195  gpio_t miso;
197 } spi_conf_t;
198 
205 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
206 
207 #ifdef __cplusplus
208 }
209 #endif
210 
211 #endif /* PERIPH_CPU_H */
212 
alternate function B
CPOL=0, CPHA=1.
Uart * dev
U(S)ART device used.
emit interrupt on rising flank
Definition: gpio.h:114
uint8_t irqn
interrupt number of the device
gpio_t mosi
pin mapped to the MOSI line
PWM channel configuration data.
gpio_mux_t
GPIO mux configuration.
Pio * rx_port
port for RX pin
Tc * dev
timer device
uint8_t tx_pin
TX pin.
gpio_mux_t mux
pin MUX setting
CPOL=0, CPHA=0.
gpio_t miso
pin mapped to the MISO line
uint8_t id_ch0
ID of the timer's first channel.
uint8_t pmc_id
bit in the PMC register of the device
uint8_t id
corresponding ID of that module
emit interrupt on both flanks
Definition: gpio.h:115
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
CPOL=1, CPHA=1.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
Spi * dev
SPI module to use.
gpio_t pin
GPIO pin connected to the channel.
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
alternate function A
uint8_t hwchan
the HW channel used for a logical channel
emit interrupt on falling flank
Definition: gpio.h:113
input, pull-up
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Configure the given GPIO pin to be used with the given MUX setting.
UART device configuration.
input, no pull
gpio_t clk
pin mapped to the CLK line
not supported
CPOL=1, CPHA=0.
SPI configuration data structure.
gpio_mux_t mux
MUX used for pins.
Pio * tx_port
port for TX pin
input, pull-down
#define GPIO_MODE(io, pu, od)
Generate GPIO mode bitfields.
uint8_t rx_pin
RX pin.
Timer configuration data.