sam3/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
22 #ifndef PERIPH_CPU_H
23 #define PERIPH_CPU_H
24 
25 #include "cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
34 #define HAVE_GPIO_T
35 typedef uint32_t gpio_t;
41 #define GPIO_UNDEF (0xffffffff)
42 
46 #define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
47 
52 #define PERIPH_SPI_NEEDS_INIT_CS
53 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
54 #define PERIPH_SPI_NEEDS_TRANSFER_REG
55 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
56 
61 #define CPUID_LEN (16U)
62 
66 #define TIMER_MAX_VAL (0xffffffff)
67 
71 #define TIMER_CHANNELS (3)
72 
81 #define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
82 
90 #define ADC_NUMOF (16U)
91 
92 #ifndef DOXYGEN
93 
97 #define HAVE_GPIO_MODE_T
98 typedef enum {
99  GPIO_IN = GPIO_MODE(0, 0, 0),
100  GPIO_IN_PD = 0xf,
101  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
102  GPIO_OUT = GPIO_MODE(1, 0, 0),
103  GPIO_OD = GPIO_MODE(1, 0, 1),
104  GPIO_OD_PU = GPIO_MODE(1, 1, 1),
105 } gpio_mode_t;
112 #define HAVE_GPIO_FLANK_T
113 typedef enum {
114  GPIO_RISING = 1,
115  GPIO_FALLING = 2,
116  GPIO_BOTH = 3
117 } gpio_flank_t;
119 #endif /* ndef DOXYGEN */
120 
124 enum {
125  PA = 0,
126  PB = 1,
127  PC = 2,
128  PD = 3,
129 };
130 
134 typedef enum {
137 } gpio_mux_t;
138 
143 #define HAVE_SPI_MODE_T
144 typedef enum {
145  SPI_MODE_0 = (SPI_CSR_NCPHA),
146  SPI_MODE_1 = (0),
147  SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA),
148  SPI_MODE_3 = (SPI_CSR_CPOL)
149 } spi_mode_t;
156 #define HAVE_SPI_CLK_T
157 typedef enum {
158  SPI_CLK_100KHZ = (100000),
159  SPI_CLK_400KHZ = (400000),
160  SPI_CLK_1MHZ = (1000000),
161  SPI_CLK_5MHZ = (5000000),
162  SPI_CLK_10MHZ = (10000000)
163 } spi_clk_t;
170 #define HAVE_ADC_RES_T
171 typedef enum {
172  ADC_RES_6BIT = 0x1,
173  ADC_RES_8BIT = 0x2,
174  ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10,
175  ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
178 } adc_res_t;
184 typedef struct {
185  Tc *dev;
186  uint8_t id_ch0;
187 } timer_conf_t;
188 
192 typedef struct {
193  Uart *dev;
194  Pio *rx_port;
195  Pio *tx_port;
196  uint8_t rx_pin;
197  uint8_t tx_pin;
199  uint8_t pmc_id;
200  uint8_t irqn;
201 } uart_conf_t;
202 
206 typedef struct {
207  gpio_t pin;
208  uint8_t hwchan;
210 
214 typedef struct {
215  Spi *dev;
216  uint8_t id;
217  gpio_t clk;
218  gpio_t mosi;
219  gpio_t miso;
221 } spi_conf_t;
222 
229 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
230 
231 #ifdef __cplusplus
232 }
233 #endif
234 
235 #endif /* PERIPH_CPU_H */
236 
alternate function B
CPOL=0, CPHA=1.
Uart * dev
U(S)ART device used.
emit interrupt on rising flank
Definition: gpio.h:114
uint8_t irqn
interrupt number of the device
gpio_t mosi
pin mapped to the MOSI line
ADC resolution: 12 bit.
PWM channel configuration data.
gpio_mux_t
GPIO mux configuration.
Pio * rx_port
port for RX pin
Tc * dev
timer device
uint8_t tx_pin
TX pin.
gpio_mux_t mux
pin MUX setting
CPOL=0, CPHA=0.
gpio_t miso
pin mapped to the MISO line
uint8_t id_ch0
ID of the timer&#39;s first channel.
uint8_t pmc_id
bit in the PMC register of the device
uint8_t id
corresponding ID of that module
emit interrupt on both flanks
Definition: gpio.h:115
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
ADC resolution: 10 bit.
CPOL=1, CPHA=1.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
Spi * dev
SPI module to use.
gpio_t pin
GPIO pin connected to the channel.
gpio_mux_t
Available MUX values for configuring a pin&#39;s alternate function.
alternate function A
uint8_t hwchan
the HW channel used for a logical channel
emit interrupt on falling flank
Definition: gpio.h:113
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Configure the given GPIO pin to be used with the given MUX setting.
UART device configuration.
input, no pull
gpio_t clk
pin mapped to the CLK line
not supported
CPOL=1, CPHA=0.
SPI configuration data structure.
gpio_mux_t mux
MUX used for pins.
Pio * tx_port
port for TX pin
input, pull-down
#define GPIO_MODE(io, pu, od)
Generate GPIO mode bitfields.
uint8_t rx_pin
RX pin.
Timer configuration data.