sam3/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * 2015 Hamburg University of Applied Sciences
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
22 #ifndef PERIPH_CPU_H
23 #define PERIPH_CPU_H
24 
25 #include "cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
34 #define HAVE_GPIO_T
35 typedef uint32_t gpio_t;
41 #define GPIO_UNDEF (0xffffffff)
42 
46 #define GPIO_PIN(x, y) (((uint32_t)PIOA + (x << 9)) | y)
47 
52 #define PERIPH_SPI_NEEDS_INIT_CS
53 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
54 #define PERIPH_SPI_NEEDS_TRANSFER_REG
55 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
56 
61 #define CPUID_LEN (16U)
62 
66 #define TIMER_MAX_VAL (0xffffffff)
67 
71 #define TIMER_CHANNELS (3)
72 
81 #define GPIO_MODE(io, pu, od) (io | (pu << 1) | (od << 2))
82 
90 #define ADC_NUMOF (16U)
91 
103 #define DAC_NUMOF (2U)
104 
105 #ifndef DOXYGEN
106 
110 #define HAVE_GPIO_MODE_T
111 typedef enum {
112  GPIO_IN = GPIO_MODE(0, 0, 0),
113  GPIO_IN_PD = 0xf,
114  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
115  GPIO_OUT = GPIO_MODE(1, 0, 0),
116  GPIO_OD = GPIO_MODE(1, 0, 1),
117  GPIO_OD_PU = GPIO_MODE(1, 1, 1),
118 } gpio_mode_t;
125 #define HAVE_GPIO_FLANK_T
126 typedef enum {
127  GPIO_RISING = 1,
128  GPIO_FALLING = 2,
129  GPIO_BOTH = 3
130 } gpio_flank_t;
132 #endif /* ndef DOXYGEN */
133 
137 enum {
138  PA = 0,
139  PB = 1,
140  PC = 2,
141  PD = 3,
142 };
143 
147 typedef enum {
150 } gpio_mux_t;
151 
156 #define HAVE_SPI_MODE_T
157 typedef enum {
158  SPI_MODE_0 = (SPI_CSR_NCPHA),
159  SPI_MODE_1 = (0),
160  SPI_MODE_2 = (SPI_CSR_CPOL | SPI_CSR_NCPHA),
161  SPI_MODE_3 = (SPI_CSR_CPOL)
162 } spi_mode_t;
169 #define HAVE_SPI_CLK_T
170 typedef enum {
171  SPI_CLK_100KHZ = (100000),
172  SPI_CLK_400KHZ = (400000),
173  SPI_CLK_1MHZ = (1000000),
174  SPI_CLK_5MHZ = (5000000),
175  SPI_CLK_10MHZ = (10000000)
176 } spi_clk_t;
183 #define HAVE_ADC_RES_T
184 typedef enum {
185  ADC_RES_6BIT = 0x1,
186  ADC_RES_8BIT = 0x2,
187  ADC_RES_10BIT = ADC_MR_LOWRES_BITS_10,
188  ADC_RES_12BIT = ADC_MR_LOWRES_BITS_12,
191 } adc_res_t;
197 typedef struct {
198  Tc *dev;
199  uint8_t id_ch0;
200 } timer_conf_t;
201 
205 typedef struct {
206  Uart *dev;
207  gpio_t rx_pin;
208  gpio_t tx_pin;
209  gpio_mux_t mux;
210  uint8_t pmc_id;
211  uint8_t irqn;
212 } uart_conf_t;
213 
217 typedef struct {
218  gpio_t pin;
219  uint8_t hwchan;
221 
225 typedef struct {
226  Spi *dev;
227  uint8_t id;
228  gpio_t clk;
229  gpio_t mosi;
230  gpio_t miso;
232 } spi_conf_t;
233 
240 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
241 
242 #ifdef __cplusplus
243 }
244 #endif
245 
246 #endif /* PERIPH_CPU_H */
247 
alternate function B
CPOL=0, CPHA=1.
Uart * dev
U(S)ART device used.
emit interrupt on rising flank
uint8_t irqn
interrupt number of the device
gpio_t mosi
pin mapped to the MOSI line
ADC resolution: 12 bit.
PWM channel configuration.
gpio_mux_t
GPIO mux configuration.
Tc * dev
timer device
gpio_mux_t mux
pin MUX setting
CPOL=0, CPHA=0.
gpio_t miso
pin mapped to the MISO line
uint8_t id_ch0
ID of the timer&#39;s first channel.
uint8_t pmc_id
bit in the PMC register of the device
uint8_t id
corresponding ID of that module
emit interrupt on both flanks
ADC resolution: 10 bit.
CPOL=1, CPHA=1.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
Spi * dev
SPI module to use.
gpio_mux_t
Available MUX values for configuring a pin&#39;s alternate function.
alternate function A
uint8_t hwchan
the HW channel used for a logical channel
emit interrupt on falling flank
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Configure the given GPIO pin to be used with the given MUX setting.
UART device configuration.
input, no pull
gpio_t clk
pin mapped to the CLK line
not supported
CPOL=1, CPHA=0.
SPI module configuration options.
input, pull-down
#define GPIO_MODE(io, pu, od)
Generate GPIO mode bitfields.
Timer configuration.