nrf5x_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2015-2017 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_COMMON_H
20 #define PERIPH_CPU_COMMON_H
21 
22 #include "cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define PROVIDES_PM_OFF
33 
38 #define CPUID_ADDR (&NRF_FICR->DEVICEID[0])
39 
42 #define CPUID_LEN (8U)
43 
49 #ifdef CPU_MODEL_NRF52840XXAA
50 #define GPIO_PIN(x,y) ((x << 5) | y)
51 #else
52 #define GPIO_PIN(x,y) ((x & 0) | y)
53 #endif
54 
63 #define GPIO_MODE(oe, ic, pr) (oe | (ic << 1) | (pr << 2))
64 
68 #define SPI_HWCS(x) (SPI_CS_UNDEF)
69 
74 #define PERIPH_SPI_NEEDS_INIT_CS
75 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
76 #define PERIPH_SPI_NEEDS_TRANSFER_REG
77 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
78 
80 #ifndef DOXYGEN
81 
90 #define HAVE_GPIO_MODE_T
91 typedef enum {
92  GPIO_IN = GPIO_MODE(0, 0, 0),
93  GPIO_IN_PD = GPIO_MODE(0, 0, 1),
94  GPIO_IN_PU = GPIO_MODE(0, 0, 3),
95  GPIO_OUT = GPIO_MODE(1, 1, 0),
96  GPIO_OD = (0xff),
97  GPIO_OD_PU = (0xfe)
98 } gpio_mode_t;
105 #define HAVE_GPIO_FLANK_T
106 typedef enum {
107  GPIO_FALLING = 2,
108  GPIO_RISING = 1,
109  GPIO_BOTH = 3
110 } gpio_flank_t;
117 #define HAVE_ADC_RES_T
118 typedef enum {
119  ADC_RES_6BIT = 0xf0,
120  ADC_RES_8BIT = 0x00,
121  ADC_RES_10BIT = 0x02,
122  ADC_RES_12BIT = 0xf1,
123  ADC_RES_14BIT = 0xf2,
124  ADC_RES_16BIT = 0xf3
125 } adc_res_t;
127 #endif /* ndef DOXYGEN */
128 
132 typedef struct {
133  NRF_TIMER_Type *dev;
134  uint8_t channels;
135  uint8_t bitmode;
136  uint8_t irqn;
137 } timer_conf_t;
138 
143 #define HAVE_SPI_MODE_T
144 typedef enum {
146  SPI_MODE_1 = SPI_CONFIG_CPHA_Msk,
147  SPI_MODE_2 = SPI_CONFIG_CPOL_Msk,
148  SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)
149 } spi_mode_t;
156 #define HAVE_SPI_CLK_T
157 typedef enum {
158  SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125,
159  SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500,
160  SPI_CLK_1MHZ = SPI_FREQUENCY_FREQUENCY_M1,
161  SPI_CLK_5MHZ = SPI_FREQUENCY_FREQUENCY_M4,
162  SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8
163 } spi_clk_t;
169 typedef struct {
170  NRF_SPI_Type *dev;
171  uint8_t sclk;
172  uint8_t mosi;
173  uint8_t miso;
174 } spi_conf_t;
175 
176 #ifdef __cplusplus
177 }
178 #endif
179 
180 #endif /* PERIPH_CPU_COMMON_H */
181 
emit interrupt on rising flank
ADC resolution: 12 bit.
NRF_TIMER_Type * dev
timer device
emit interrupt on both flanks
not supported by hardware
ADC resolution: 10 bit.
NRF_SPI_Type * dev
SPI device used.
#define GPIO_MODE(oe, ic, pr)
Generate GPIO mode bitfields.
not supported by hardware
uint8_t channels
number of channels available
not supported by hardware
not supported by hardware
emit interrupt on falling flank
input, no pull
not supported
SPI module configuration options.
input, pull-down
Timer configuration.