nrf5x_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2015-2017 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_COMMON_H
20 #define PERIPH_CPU_COMMON_H
21 
22 #include "cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
31 #define CPUID_ADDR (&NRF_FICR->DEVICEID[0])
32 
35 #define CPUID_LEN (8U)
36 
42 #ifdef CPU_MODEL_NRF52840XXAA
43 #define GPIO_PIN(x,y) ((x << 5) | y)
44 #else
45 #define GPIO_PIN(x,y) ((x & 0) | y)
46 #endif
47 
56 #define GPIO_MODE(oe, ic, pr) (oe | (ic << 1) | (pr << 2))
57 
61 #define SPI_HWCS(x) (SPI_CS_UNDEF)
62 
67 #define PERIPH_SPI_NEEDS_INIT_CS
68 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
69 #define PERIPH_SPI_NEEDS_TRANSFER_REG
70 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
71 
73 #ifndef DOXYGEN
74 
83 #define HAVE_GPIO_MODE_T
84 typedef enum {
85  GPIO_IN = GPIO_MODE(0, 0, 0),
86  GPIO_IN_PD = GPIO_MODE(0, 0, 1),
87  GPIO_IN_PU = GPIO_MODE(0, 0, 3),
88  GPIO_OUT = GPIO_MODE(1, 1, 0),
89  GPIO_OD = (0xff),
90  GPIO_OD_PU = (0xfe)
91 } gpio_mode_t;
98 #define HAVE_GPIO_FLANK_T
99 typedef enum {
100  GPIO_FALLING = 2,
101  GPIO_RISING = 1,
102  GPIO_BOTH = 3
103 } gpio_flank_t;
110 #define HAVE_ADC_RES_T
111 typedef enum {
112  ADC_RES_6BIT = 0xf0,
113  ADC_RES_8BIT = 0x00,
114  ADC_RES_10BIT = 0x02,
115  ADC_RES_12BIT = 0xf1,
116  ADC_RES_14BIT = 0xf2,
117  ADC_RES_16BIT = 0xf3
118 } adc_res_t;
120 #endif /* ndef DOXYGEN */
121 
125 typedef struct {
126  NRF_TIMER_Type *dev;
127  uint8_t channels;
128  uint8_t bitmode;
129  uint8_t irqn;
130 } timer_conf_t;
131 
136 #define HAVE_SPI_MODE_T
137 typedef enum {
139  SPI_MODE_1 = SPI_CONFIG_CPHA_Msk,
140  SPI_MODE_2 = SPI_CONFIG_CPOL_Msk,
141  SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)
142 } spi_mode_t;
149 #define HAVE_SPI_CLK_T
150 typedef enum {
151  SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125,
152  SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500,
153  SPI_CLK_1MHZ = SPI_FREQUENCY_FREQUENCY_M1,
154  SPI_CLK_5MHZ = SPI_FREQUENCY_FREQUENCY_M4,
155  SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8
156 } spi_clk_t;
162 typedef struct {
163  NRF_SPI_Type *dev;
164  uint8_t sclk;
165  uint8_t mosi;
166  uint8_t miso;
167 } spi_conf_t;
168 
169 #ifdef __cplusplus
170 }
171 #endif
172 
173 #endif /* PERIPH_CPU_COMMON_H */
174 
emit interrupt on rising flank
Definition: gpio.h:114
ADC resolution: 12 bit.
NRF_TIMER_Type * dev
timer device
emit interrupt on both flanks
Definition: gpio.h:115
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
ADC resolution: 14 bit (not supported)
ADC resolution: 10 bit.
NRF_SPI_Type * dev
SPI device used.
#define GPIO_MODE(oe, ic, pr)
Generate GPIO mode bitfields.
ADC resolution: 16 bit (not supported)
uint8_t channels
number of channels available
ADC resolution: 8 bit.
ADC resolution: 6 bit.
emit interrupt on falling flank
Definition: gpio.h:113
input, pull-up
input, no pull
not supported
SPI configuration data structure.
input, pull-down
Timer configuration data.