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nrf5x_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2015-2017 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_COMMON_H
20 #define PERIPH_CPU_COMMON_H
21 
22 #include "cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
31 #define CPUID_LEN (8U)
32 
38 #define GPIO_PIN(x,y) ((x & 0) | y)
39 
48 #define GPIO_MODE(oe, ic, pr) (oe | (ic << 1) | (pr << 2))
49 
53 #define SPI_HWCS(x) (SPI_CS_UNDEF)
54 
59 #define PERIPH_SPI_NEEDS_INIT_CS
60 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
61 #define PERIPH_SPI_NEEDS_TRANSFER_REG
62 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
63 
65 #ifndef DOXYGEN
66 
75 #define HAVE_GPIO_MODE_T
76 typedef enum {
77  GPIO_IN = GPIO_MODE(0, 0, 0),
78  GPIO_IN_PD = GPIO_MODE(0, 0, 1),
79  GPIO_IN_PU = GPIO_MODE(0, 0, 3),
80  GPIO_OUT = GPIO_MODE(1, 1, 0),
81  GPIO_OD = (0xff),
82  GPIO_OD_PU = (0xfe)
83 } gpio_mode_t;
90 #define HAVE_GPIO_FLANK_T
91 typedef enum {
92  GPIO_FALLING = 2,
93  GPIO_RISING = 1,
94  GPIO_BOTH = 3
95 } gpio_flank_t;
102 #define HAVE_ADC_RES_T
103 typedef enum {
104  ADC_RES_6BIT = 0xf0,
105  ADC_RES_8BIT = 0x00,
106  ADC_RES_10BIT = 0x02,
107  ADC_RES_12BIT = 0xf1,
108  ADC_RES_14BIT = 0xf2,
109  ADC_RES_16BIT = 0xf3
110 } adc_res_t;
112 #endif /* ndef DOXYGEN */
113 
117 typedef struct {
118  NRF_TIMER_Type *dev;
119  uint8_t channels;
120  uint8_t bitmode;
121  uint8_t irqn;
122 } timer_conf_t;
123 
128 #define HAVE_SPI_MODE_T
129 typedef enum {
131  SPI_MODE_1 = SPI_CONFIG_CPHA_Msk,
132  SPI_MODE_2 = SPI_CONFIG_CPOL_Msk,
133  SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)
134 } spi_mode_t;
141 #define HAVE_SPI_CLK_T
142 typedef enum {
143  SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125,
144  SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500,
145  SPI_CLK_1MHZ = SPI_FREQUENCY_FREQUENCY_M1,
146  SPI_CLK_5MHZ = SPI_FREQUENCY_FREQUENCY_M4,
147  SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8
148 } spi_clk_t;
154 typedef struct {
155  NRF_SPI_Type *dev;
156  uint8_t sclk;
157  uint8_t mosi;
158  uint8_t miso;
159 } spi_conf_t;
160 
161 #ifdef __cplusplus
162 }
163 #endif
164 
165 #endif /* PERIPH_CPU_COMMON_H */
166 
emit interrupt on rising flank
Definition: gpio.h:114
ADC resolution: 12 bit.
NRF_TIMER_Type * dev
timer device
emit interrupt on both flanks
Definition: gpio.h:115
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
ADC resolution: 14 bit (not supported)
ADC resolution: 10 bit.
NRF_SPI_Type * dev
SPI device used.
#define GPIO_MODE(oe, ic, pr)
Generate GPIO mode bitfields.
ADC resolution: 16 bit (not supported)
uint8_t channels
number of channels available
ADC resolution: 8 bit.
ADC resolution: 6 bit.
emit interrupt on falling flank
Definition: gpio.h:113
input, pull-up
input, no pull
not supported
SPI configuration data structure.
input, pull-down
Timer configuration data.