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usbdev_synopsys_dwc2.h
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1/*
2 * Copyright (C) 2019 Koen Zandberg
3 * 2022 Gunar Schorcht
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
10#pragma once
11
23#include <stdint.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
35#define USBDEV_CPU_SET_ADDR_AFTER_STATUS 0
36
50
54enum {
59};
60
75
79typedef struct {
80 uintptr_t periph;
83#if defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN
97#endif
98#if defined(CPU_STM32) || DOXYGEN
99 uint32_t rcc_mask;
100 uint8_t irqn;
101 uint8_t ahb;
105#if defined(MODULE_PERIPH_USBDEV_HS_UTMI) || DOXYGEN
106 uint32_t phy_tune;
109#endif /* defined(MODULE_PERIPH_USBDEV_HS_UTMI) */
110#endif /* defined(CPU_STM32) || DOXYGEN */
111#if defined(CPU_GD32V)
112 uint32_t rcu_mask;
113 uint8_t irqn;
114 uint8_t bus;
115#endif
117
118#ifdef __cplusplus
119}
120#endif
121
gpio_af_t
Override alternative GPIO mode options.
Definition periph_cpu.h:166
uint16_t gpio_t
GPIO type identifier.
Definition periph_cpu.h:117
gpio_af_t af
Alternative function.
uintptr_t periph
USB peripheral base address.
dwc2_usb_otg_fshs_type_t type
FS or HS type.
uint32_t rcc_mask
bit in clock enable register
dwc2_usb_otg_fshs_phy_t phy
on-chip FS, ULPI HS or UTMI HS PHY
uint32_t phy_tune
USB HS PHY controller tuning register value (STM32-specific), see USBPHYC_TUNE register in STM32 Refe...
gpio_af_t ulpi_af
Alternative function for ULPI.
dwc2_usb_otg_fshs_phy_t
Type of USB OTG peripheral PHY.
@ DWC2_USB_OTG_PHY_ULPI
ULPI for external HS PHY.
@ DWC2_USB_OTG_PHY_UTMI
UTMI for internal HS PHY.
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
@ DWC2_USB_OTG_DSPD_HS
High speed.
@ DWC2_USB_OTG_DSPD_LS
Low speed.
@ DWC2_USB_OTG_DSPD_FS
Full speed.
@ DWC2_USB_OTG_DSPD_FS_PHY_HS
Full speed on HS PHY.
dwc2_usb_otg_fshs_type_t
USB OTG peripheral type.
@ DWC2_USB_OTG_FS
Full speed peripheral.
@ DWC2_USB_OTG_HS
High speed peripheral.