periph_cpu.h File Reference

Shared CPU specific definitions for the STM32 family. More...

Detailed Description

Shared CPU specific definitions for the STM32 family.

Author
Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de
Vincent Dupont vince.nosp@m.nt@o.nosp@m.takey.nosp@m.s.co.nosp@m.m

Definition in file periph_cpu.h.

#include "cpu.h"
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Go to the source code of this file.

Data Structures

struct  dma_conf_t
 DMA configuration. More...
 
struct  adc_conf_t
 ADC device configuration. More...
 
struct  dac_conf_t
 DAC line configuration data. More...
 
struct  timer_conf_t
 Timer configuration. More...
 
struct  pwm_chan_t
 PWM channel. More...
 
struct  pwm_conf_t
 PWM device configuration. More...
 
struct  qdec_chan_t
 QDEC channel. More...
 
struct  qdec_conf_t
 QDEC configuration. More...
 
struct  uart_conf_t
 UART device configuration. More...
 
struct  spi_conf_t
 SPI configuration structure type. More...
 
struct  i2c_conf_t
 I2C configuration options. More...
 
struct  stm32_usb_otg_fshs_config_t
 stm32 USB OTG configuration More...
 
struct  eth_conf_t
 Ethernet Peripheral configuration. More...
 

Macros

#define PM_EWUP_CONFIG   (0U)
 Wake-up pins configuration (CSR register)
 
#define GPIO_UNDEF   (0xffffffff)
 Definition of a fitting UNDEF value.
 
#define GPIO_PIN(x, y)   ((GPIOA_BASE + (x << 10)) | y)
 Define a CPU specific GPIO pin generator macro.
 
#define SPI_HWCS_MASK   (0xffffff00)
 Define a magic number that tells us to use hardware chip select. More...
 
#define SPI_HWCS(x)   (SPI_HWCS_MASK | x)
 Override the default SPI hardware chip select access macro. More...
 
#define GPIO_MODE(io, pr, ot)   ((io << 0) | (pr << 2) | (ot << 4))
 Generate GPIO mode bitfields. More...
 
#define UART_TXBUF_SIZE   (64)
 Size of the UART TX buffer for non-blocking mode.
 

Typedefs

typedef unsigned dma_t
 DMA type.
 

Enumerations

enum  bus_t { APB1, APB2 }
 Available peripheral buses. More...
 
enum  {
  PORT_A = 0, PORT_B = 1, PORT_C = 2, PORT_D = 3,
  PORT_E = 4, PORT_F = 5
}
 Available GPIO ports. More...
 
enum  gpio_af_t {
  GPIO_AF0 = 0, GPIO_AF1, GPIO_AF2, GPIO_AF3,
  GPIO_AF4, GPIO_AF5, GPIO_AF6, GPIO_AF7,
  GPIO_AF8, GPIO_AF9, GPIO_AF10, GPIO_AF11,
  GPIO_AF12, GPIO_AF13, GPIO_AF14, GPIO_AF15,
  GPIO_AF0 = 0, GPIO_AF1, GPIO_AF2, GPIO_AF3,
  GPIO_AF4, GPIO_AF5, GPIO_AF6, GPIO_AF7,
  GPIO_AF8, GPIO_AF9, GPIO_AF10, GPIO_AF11,
  GPIO_AF12, GPIO_AF13, GPIO_AF14, GPIO_AF15
}
 Available MUX values for configuring a pin's alternate function. More...
 
enum  dma_mode_t { DMA_PERIPH_TO_MEM = 0, DMA_MEM_TO_PERIPH = 1, DMA_MEM_TO_MEM = 2 }
 DMA modes. More...
 
enum  uart_type_t { KINETIS_UART, KINETIS_LPUART, STM32_USART, STM32_LPUART }
 UART hardware module types. More...
 
enum  stm32_usb_otg_fshs_type_t { STM32_USB_OTG_FS = 0, STM32_USB_OTG_HS = 1 }
 USB OTG peripheral type. More...
 
enum  stm32_usb_otg_fshs_phy_t { STM32_USB_OTG_PHY_BUILTIN, STM32_USB_OTG_PHY_ULPI }
 Type of USB OTG peripheral phy. More...
 
enum  eth_mode_t { MII = 18, RMII = 9, SMI = 2 }
 STM32 Ethernet configuration mode. More...
 
enum  eth_speed_t { ETH_SPEED_10T_HD = 0x0000, ETH_SPEED_10T_FD = 0x0100, ETH_SPEED_100TX_HD = 0x2000, ETH_SPEED_100TX_FD = 0x2100 }
 STM32 Ethernet speed options.
 

Functions

uint32_t periph_apb_clk (uint8_t bus)
 Get the actual bus clock frequency for the APB buses. More...
 
uint32_t periph_timer_clk (uint8_t bus)
 Get the actual timer clock frequency. More...
 
void periph_clk_en (bus_t bus, uint32_t mask)
 Enable the given peripheral clock. More...
 
void periph_lpclk_dis (bus_t bus, uint32_t mask)
 Disable the given peripheral clock. More...
 
void periph_lpclk_en (bus_t bus, uint32_t mask)
 Enable the given peripheral clock in low power mode. More...
 
void periph_clk_dis (bus_t bus, uint32_t mask)
 Disable the given peripheral clock in low power mode. More...
 
void gpio_init_af (gpio_t pin, gpio_af_t af)
 Configure the alternate function for the given pin. More...
 
void gpio_init_analog (gpio_t pin)
 Configure the given pin to be used as ADC input. More...
 
#define CPUID_LEN   (12U)
 CPU specific LSI clock speed. More...
 
#define CPUID_ADDR   (UID_BASE)
 Starting address of the CPU ID.
 
#define PROVIDES_PM_LAYERED_OFF
 We provide our own pm_off() function for all STM32-based CPUs.
 
#define TIMER_CHANNEL_NUMOF   (4U)
 All STM timers have 4 capture-compare channels.
 
#define TIM_CHAN(tim, chan)   *(&dev(tim)->CCR1 + chan)
 Define a macro for accessing a timer channel.
 
#define QDEC_CHAN   (2U)
 All STM QDEC timers have 2 capture channels.
 
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
 Use the shared SPI functions.
 
#define PERIPH_SPI_NEEDS_TRANSFER_REG
 
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 

PM definitions

#define PM_NUM_MODES   (2U)
 Number of usable low power modes.
 

Power modes

#define STM32_PM_STOP   (1U)
 
#define STM32_PM_STANDBY   (0U)
 

WDT upper and lower bound times in ms

#define NWDT_TIME_LOWER_LIMIT   (1U)
 
#define NWDT_TIME_UPPER_LIMIT
 
#define WDT_HAS_STOP   (0U)
 
#define WDT_HAS_INIT   (0U)
 

Use the shared I2C functions

#define PERIPH_I2C_NEED_READ_REG
 Use read reg function from periph common.
 
#define PERIPH_I2C_NEED_WRITE_REG
 Use write reg function from periph common.
 
#define PERIPH_I2C_NEED_READ_REGS
 

DMA Increment modes

#define DMA_INC_SRC_ADDR   (0x04)
 
#define DMA_INC_DST_ADDR   (0x08)
 
#define DMA_INC_BOTH_ADDR   (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
 

DMA data width

#define DMA_DATA_WIDTH_BYTE   (0x00)
 
#define DMA_DATA_WIDTH_HALF_WORD   (0x01)
 
#define DMA_DATA_WIDTH_WORD   (0x02)
 
#define DMA_DATA_WIDTH_MASK   (0x03)
 
#define DMA_DATA_WIDTH_SHIFT   (0)
 

Ethernet PHY Common Registers

#define PHY_BMCR   (0x00)
 
#define PHY_BSMR   (0x01)
 
#define PHY_PHYIDR1   (0x02)
 
#define PHY_PHYIDR2   (0x03)
 
#define PHY_ANAR   (0x04)
 
#define PHY_ANLPAR   (0x05)
 
#define PHY_ANER   (0x06)
 
#define PHY_ANNPTR   (0x07)
 

Ethernet PHY BMCR Fields

#define BMCR_RESET   (0x8000)
 
#define BMCR_LOOPBACK   (0x4000)
 
#define BMCR_SPEED_SELECT   (0x2000)
 
#define BMCR_AN   (0x1000)
 
#define BMCR_POWER_DOWN   (0x0800)
 
#define BMCR_ISOLATE   (0x0400)
 
#define BMCR_RESTART_AN   (0x0200)
 
#define BMCR_DUPLEX_MODE   (0x0100)
 
#define BMCR_COLLISION_TEST   (0x0080)
 

Ethernet PHY BSMR Fields

#define BSMR_100BASE_T4   (0x8000)
 
#define BSMR_100BASE_TX_FDUPLEX   (0x4000)
 
#define BSMR_100BASE_TX_HDUPLEX   (0x2000)
 
#define BSMR_10BASE_T_FDUPLEX   (0x1000)
 
#define BSMR_10BASE_T_HDUPLEX   (0x0800)
 
#define BSMR_NO_PREAMBLE   (0x0040)
 
#define BSMR_AN_COMPLETE   (0x0020)
 
#define BSMR_REMOTE_FAULT   (0x0010)
 
#define BSMR_AN_ABILITY   (0x0008)
 
#define BSMR_LINK_STATUS   (0x0004)
 
#define BSMR_JABBER_DETECT   (0x0002)
 
#define BSMR_EXTENDED_CAP   (0x0001)
 

Ethernet PHY PHYIDR1 Fields

#define PHYIDR1_OUI   (0xffff)
 

Ethernet PHY PHYIDR2 Fields

#define PHYIDR2_OUI   (0xfe00)
 
#define PHYIDR2_MODEL   (0x01f0)
 
#define PHYIDR2_REV   (0x0007)
 

Ethernet PHY ANAR Fields

#define ANAR_NEXT_PAGE   (0x8000)
 
#define ANAR_REMOTE_FAULT   (0x2000)
 
#define ANAR_PAUSE   (0x0600)
 
#define ANAR_100BASE_T4   (0x0200)
 
#define ANAR_100BASE_TX_FDUPLEX   (0x0100)
 
#define ANAR_100BASE_TX_HDUPLEX   (0x0080)
 
#define ANAR_10BASE_T_FDUPLEX   (0x0040)
 
#define ANAR_10BASE_T_HDUPLEX   (0x0020)
 
#define ANAR_SELECTOR   (0x000f)
 

Ethernet PHY ANLPAR Fields

#define ANLPAR_NEXT_PAGE   (0x8000)
 
#define ANLPAR_ACK   (0x4000)
 
#define ANLPAR_REMOTE_FAULT   (0x2000)
 
#define ANLPAR_PAUSE   (0x0600)
 
#define ANLPAR_100BASE_T4   (0x0200)
 
#define ANLPAR_100BASE_TX_FDUPLEX   (0x0100)
 
#define ANLPAR_100BASE_TX_HDUPLEX   (0x0080)
 
#define ANLPAR_10BASE_T_FDUPLEX   (0x0040)
 
#define ANLPAR_10BASE_T_HDUPLEX   (0x0020)
 
#define ANLPAR_SELECTOR   (0x000f)
 

Ethernet PHY ANNPTR Fields

#define ANNPTR_NEXT_PAGE   (0x8000)
 
#define ANNPTR_MSG_PAGE   (0x2000)
 
#define ANNPTR_ACK2   (0x1000)
 
#define ANNPTR_TOGGLE_TX   (0x0800)
 
#define ANNPTR_CODE   (0x03ff)
 

Ethernet PHY ANER Fields

#define ANER_PDF   (0x0010)
 
#define ANER_LP_NEXT_PAGE_ABLE   (0x0008)
 
#define ANER_NEXT_PAGE_ABLE   (0x0004)
 
#define ANER_PAGE_RX   (0x0002)
 
#define ANER_LP_AN_ABLE   (0x0001)
 

Macro Definition Documentation

◆ CPUID_LEN

#define CPUID_LEN   (12U)

CPU specific LSI clock speed.

Length of the CPU_ID in octets

This is the same for all members of the stm32 family

Definition at line 83 of file periph_cpu.h.

◆ GPIO_MODE

#define GPIO_MODE (   io,
  pr,
  ot 
)    ((io << 0) | (pr << 2) | (ot << 4))

Generate GPIO mode bitfields.

We use 5 bit to encode the mode:

  • bit 0+1: pin mode (input / output)
  • bit 2+3: pull resistor configuration
  • bit 4: output type (0: push-pull, 1: open-drain)

Definition at line 358 of file periph_cpu.h.

◆ NWDT_TIME_UPPER_LIMIT

#define NWDT_TIME_UPPER_LIMIT
Value:
(4U * US_PER_MS * 4096U * (1 << 6U) \
/ CLOCK_LSI)
#define US_PER_MS
The number of microseconds per millisecond.
Definition: timex.h:54

Definition at line 152 of file periph_cpu.h.

◆ SPI_HWCS

#define SPI_HWCS (   x)    (SPI_HWCS_MASK | x)

Override the default SPI hardware chip select access macro.

Since the CPU does only support one single hardware chip select line, we can detect the usage of non-valid lines by comparing to SPI_HWCS_VALID.

Definition at line 261 of file periph_cpu.h.

◆ SPI_HWCS_MASK

#define SPI_HWCS_MASK   (0xffffff00)

Define a magic number that tells us to use hardware chip select.

We use a random value here, that does clearly differentiate from any possible GPIO_PIN(x) value.

Definition at line 253 of file periph_cpu.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Available GPIO ports.

Enumerator
PORT_A 

port A

PORT_B 

port B

PORT_C 

port C

PORT_D 

port D

PORT_E 

port E

PORT_F 

port F

Definition at line 216 of file periph_cpu.h.

◆ bus_t

enum bus_t

Available peripheral buses.

Enumerator
APB1 

APB1 bus.

APB2 

APB2 bus.

Definition at line 166 of file periph_cpu.h.

◆ dma_mode_t

enum dma_mode_t

DMA modes.

Enumerator
DMA_PERIPH_TO_MEM 

Peripheral to memory.

DMA_MEM_TO_PERIPH 

Memory to peripheral.

DMA_MEM_TO_MEM 

Memory to memory.

Definition at line 429 of file periph_cpu.h.

◆ eth_mode_t

enum eth_mode_t

STM32 Ethernet configuration mode.

Enumerator
MII 

Configuration for MII.

RMII 

Configuration for RMII.

SMI 

Configuration for SMI.

Definition at line 986 of file periph_cpu.h.

◆ gpio_af_t

enum gpio_af_t

Available MUX values for configuring a pin's alternate function.

Enumerator
GPIO_AF0 

use alternate function 0

GPIO_AF1 

use alternate function 1

GPIO_AF2 

use alternate function 2

GPIO_AF3 

use alternate function 3

GPIO_AF4 

use alternate function 4

GPIO_AF5 

use alternate function 5

GPIO_AF6 

use alternate function 6

GPIO_AF7 

use alternate function 7

GPIO_AF8 

use alternate function 8

GPIO_AF9 

use alternate function 9

GPIO_AF10 

use alternate function 10

GPIO_AF11 

use alternate function 11

GPIO_AF12 

use alternate function 12

GPIO_AF13 

use alternate function 13

GPIO_AF14 

use alternate function 14

GPIO_AF15 

use alternate function 15

GPIO_AF0 

use alternate function 0

GPIO_AF1 

use alternate function 1

GPIO_AF2 

use alternate function 2

GPIO_AF3 

use alternate function 3

GPIO_AF4 

use alternate function 4

GPIO_AF5 

use alternate function 5

GPIO_AF6 

use alternate function 6

GPIO_AF7 

use alternate function 7

GPIO_AF8 

use alternate function 8

GPIO_AF9 

use alternate function 9

GPIO_AF10 

use alternate function 10

GPIO_AF11 

use alternate function 11

GPIO_AF12 

use alternate function 12

GPIO_AF13 

use alternate function 13

GPIO_AF14 

use alternate function 14

GPIO_AF15 

use alternate function 15

Definition at line 281 of file periph_cpu.h.

◆ stm32_usb_otg_fshs_phy_t

Type of USB OTG peripheral phy.

The FS type only supports the built-in type, the HS phy can have either the FS built-in phy enabled or the HS ULPI interface enabled.

Definition at line 764 of file periph_cpu.h.

◆ stm32_usb_otg_fshs_type_t

USB OTG peripheral type.

High speed peripheral is assumed to have DMA support available.

Warning
Only one of each type is supported at the moment, it is not supported to have two FS type or two HS type peripherals enabled on a single MCU.
Enumerator
STM32_USB_OTG_FS 

Full speed peripheral.

STM32_USB_OTG_HS 

High speed peripheral.

Definition at line 753 of file periph_cpu.h.

◆ uart_type_t

UART hardware module types.

Enumerator
KINETIS_UART 

Kinetis UART module type.

KINETIS_LPUART 

Kinetis Low-power UART (LPUART) module type.

STM32_USART 

STM32 USART module type.

STM32_LPUART 

STM32 Low-power UART (LPUART) module type.

Definition at line 551 of file periph_cpu.h.

Function Documentation

◆ gpio_init_af()

void gpio_init_af ( gpio_t  pin,
gpio_af_t  af 
)

Configure the alternate function for the given pin.

Parameters
[in]pinpin to configure
[in]afalternate function to use

◆ gpio_init_analog()

void gpio_init_analog ( gpio_t  pin)

Configure the given pin to be used as ADC input.

Parameters
[in]pinpin to configure

◆ periph_apb_clk()

uint32_t periph_apb_clk ( uint8_t  bus)

Get the actual bus clock frequency for the APB buses.

Parameters
[in]bustarget APBx bus
Returns
bus clock frequency in Hz

◆ periph_clk_dis()

void periph_clk_dis ( bus_t  bus,
uint32_t  mask 
)

Disable the given peripheral clock in low power mode.

Parameters
[in]busbus the peripheral is connected to
[in]maskbit in the RCC enable register

◆ periph_clk_en()

void periph_clk_en ( bus_t  bus,
uint32_t  mask 
)

Enable the given peripheral clock.

Parameters
[in]busbus the peripheral is connected to
[in]maskbit in the RCC enable register

◆ periph_lpclk_dis()

void periph_lpclk_dis ( bus_t  bus,
uint32_t  mask 
)

Disable the given peripheral clock.

Parameters
[in]busbus the peripheral is connected to
[in]maskbit in the RCC enable register

◆ periph_lpclk_en()

void periph_lpclk_en ( bus_t  bus,
uint32_t  mask 
)

Enable the given peripheral clock in low power mode.

Parameters
[in]busbus the peripheral is connected to
[in]maskbit in the RCC enable register

◆ periph_timer_clk()

uint32_t periph_timer_clk ( uint8_t  bus)

Get the actual timer clock frequency.

Parameters
[in]buscorresponding APBx bus
Returns
timer clock frequency in Hz