Loading...
Searching...
No Matches
periph_cpu.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2016 Freie Universität Berlin
3 * 2017 OTA keys S.A.
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CPU_H
22#define PERIPH_CPU_H
23
24#include <limits.h>
25
26#include "cpu.h"
27#include "macros/units.h"
28
29#if defined(CPU_FAM_STM32F0)
31#elif defined(CPU_FAM_STM32F1)
33#elif defined(CPU_FAM_STM32F2)
35#elif defined(CPU_FAM_STM32F3)
37#elif defined(CPU_FAM_STM32F4)
39#elif defined(CPU_FAM_STM32F7)
41#elif defined(CPU_FAM_STM32G0)
43#elif defined(CPU_FAM_STM32C0)
45#elif defined(CPU_FAM_STM32G4)
47#elif defined(CPU_FAM_STM32L0)
49#elif defined(CPU_FAM_STM32L1)
51#elif defined(CPU_FAM_STM32L4)
53#elif defined(CPU_FAM_STM32L5)
55#elif defined(CPU_FAM_STM32U5)
57#elif defined(CPU_FAM_STM32WB)
59#elif defined(CPU_FAM_STM32WL)
61#endif
62
64#include "periph/cpu_common.h"
65#include "periph/cpu_dma.h"
66#include "periph/cpu_eth.h"
67#include "periph/cpu_fmc.h"
68#include "periph/cpu_gpio.h"
69#include "periph/cpu_gpio_ll.h"
70#include "periph/cpu_i2c.h"
71#include "periph/cpu_ltdc.h"
72#include "periph/cpu_pm.h"
73#include "periph/cpu_pwm.h"
74#include "periph/cpu_qdec.h"
75#include "periph/cpu_sdmmc.h"
76#include "periph/cpu_spi.h"
77#include "periph/cpu_timer.h"
78#include "periph/cpu_uart.h"
79#include "periph/cpu_usbdev.h"
80#include "periph/cpu_vbat.h"
81#include "periph/cpu_wdt.h"
82
83#ifdef MODULE_PERIPH_CAN
84#include "candev_stm32.h"
85#endif
86
87#ifdef __cplusplus
88extern "C" {
89#endif
90
94typedef struct {
95 gpio_t pin;
96#if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
97 !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32WL)
98 uint8_t dev;
99#endif
100 uint8_t chan;
101} adc_conf_t;
102
106typedef struct {
107 gpio_t pin;
108 uint8_t chan;
109} dac_conf_t;
110
115#define HAVE_PTP_CLOCK_READ 1
116#define HAVE_PTP_CLOCK_SET 1
117#define HAVE_PTP_TIMER_SET_ABSOLUTE 1
120#if !DOXYGEN /* hide implementation details */
125/* Detect the IP version based on the available register define */
126#if defined(USB_OTG_GCCFG_NOVBUSSENS)
127#define STM32_USB_OTG_CID_1x
128#elif defined(USB_OTG_GCCFG_VBDEN)
129#define STM32_USB_OTG_CID_2x
130#elif defined(USB)
131#define STM32_USB_FS_CID_1x
132#endif
133
138#if defined(USB_OTG_FS_MAX_IN_ENDPOINTS)
139#define STM32_USB_OTG_FS_NUM_EP (USB_OTG_FS_MAX_IN_ENDPOINTS)
140#elif defined(STM32_USB_OTG_CID_1x)
141#define STM32_USB_OTG_FS_NUM_EP (4)
142#elif defined(STM32_USB_OTG_CID_2x)
143#define STM32_USB_OTG_FS_NUM_EP (6)
144#endif
145
150#if defined(USB_OTG_HS_MAX_IN_ENDPOINTS)
151#define STM32_USB_OTG_HS_NUM_EP (USB_OTG_HS_MAX_IN_ENDPOINTS)
152#elif defined(STM32_USB_OTG_CID_1x)
153#define STM32_USB_OTG_HS_NUM_EP (6)
154#elif defined(STM32_USB_OTG_CID_2x)
155#define STM32_USB_OTG_HS_NUM_EP (9)
156#endif
157
168#if defined(MODULE_PERIPH_USBDEV_HS) && defined(STM32_USB_OTG_HS_NUM_EP)
169#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_HS_NUM_EP
170#elif defined(STM32_USB_OTG_FS_NUM_EP)
171#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_FS_NUM_EP
172#else
173#define USBDEV_NUM_ENDPOINTS 8
174#endif
175
176/* unify names across STM32 families */
177#ifdef SPI_CR1_CPHA_Msk
178# define STM32_SPI_CPHA_Msk SPI_CR1_CPHA_Msk
179#endif
180#ifdef SPI_CFG2_CPHA_Msk
181# define STM32_SPI_CPHA_Msk SPI_CFG2_CPHA_Msk
182#endif
183#ifdef SPI_CR1_CPOL_Msk
184# define STM32_SPI_CPOL_Msk SPI_CR1_CPOL_Msk
185#endif
186#ifdef SPI_CFG2_CPOL_Msk
187# define STM32_SPI_CPOL_Msk SPI_CFG2_CPOL_Msk
188#endif
189
197#define HAVE_SPI_MODE_T
198typedef enum {
199 SPI_MODE_0 = 0,
200 SPI_MODE_1 = STM32_SPI_CPHA_Msk,
201 SPI_MODE_2 = STM32_SPI_CPOL_Msk,
202 SPI_MODE_3 = STM32_SPI_CPOL_Msk | STM32_SPI_CPHA_Msk,
203} spi_mode_t;
206#endif /* !DOXYGEN */
207
208#ifdef __cplusplus
209}
210#endif
211
212#endif /* PERIPH_CPU_H */
bxCAN specific definitions
gpio_t adc_conf_t
ADC configuration wrapper.
Definition periph_cpu.h:337
Backup SRAM CPU specific definitions for the STM32 family.
DMA CPU specific definitions for the STM32 family.
Ethernet CPU specific definitions for the STM32 family.
Specific FMC definitions for the STM32.
GPIO CPU definitions for the STM32 family.
GPIO LL CPU definitions for the STM32 family.
I2C CPU specific definitions for the STM32 family.
LTDC CPU specific definitions for the STM32 family.
PWM CPU specific definitions for the STM32 family.
QDEC CPU specific definitions for the STM32 family.
CPU specific definitions for SDIO/SDMMC for the STM32 family.
SPI CPU specific definitions for the STM32 family.
Timer CPU specific definitions for the STM32 family.
UART CPU specific definitions for the STM32 family.
USB CPU specific definitions for the STM32 family.
CPU internal VBAT interface and definitions of the STM32 family.
Watchdog CPU definitions for the STM32 family.
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
STM32C0 CPU specific definitions for internal peripheral handling.
Common CPU definitions for the STM32 family.
Power Management (PM) CPU specific definitions for the STM32 family.
STM32F0 CPU specific definitions for internal peripheral handling.
STM32F1 CPU specific definitions for internal peripheral handling.
STM32F2 CPU specific definitions for internal peripheral handling.
STM32F3 CPU specific definitions for internal peripheral handling.
STM32F4 CPU specific definitions for internal peripheral handling.
STM32F7 CPU specific definitions for internal peripheral handling.
STM32G0 CPU specific definitions for internal peripheral handling.
STM3G4 CPU specific definitions for internal peripheral handling.
STM32L0 CPU specific definitions for internal peripheral handling.
STM32L1 CPU specific definitions for internal peripheral handling.
STM32L4 CPU specific definitions for internal peripheral handling.
STM32L5 CPU specific definitions for internal peripheral handling.
STM32U5 CPU specific definitions for internal peripheral handling.
STM32WB CPU specific definitions for internal peripheral handling.
STM32WL CPU specific definitions for internal peripheral handling.
DAC line configuration data.
Definition periph_cpu.h:301
Unit helper macros.