Loading...
Searching...
No Matches
cc26xx_cc13xx.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2016 Leon George
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef CC26XX_CC13XX_H
21#define CC26XX_CC13XX_H
22
23#include <stdint.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
32typedef volatile uint8_t reg8_t;
36typedef volatile uint16_t reg16_t;
40typedef volatile uint32_t reg32_t;
41
45typedef struct {
48} reg8_m4_t;
49
54
58typedef struct {
62
70typedef enum IRQn {
71 /****** Cortex-M4 Processor Exceptions Numbers ****************************/
83 /****** CC13x2 specific Interrupt Numbers *********************************/
96 I2S_IRQN = 12,
111 SW0_IRQN = 27,
118#ifdef CPU_VARIANT_X2
119 OSC_IRQN = 34,
120 AUX_TIMER2_IRQN = 35,
121 UART1_IRQN = 36,
122 BATMON_IRQN = 37,
124 IRQN_COUNT = (BATMON_IRQN + 1)
125#else
126 IRQN_COUNT = (TRNG_IRQN + 1)
127#endif
128
130
135#define __MPU_PRESENT 1
136#define __NVIC_PRIO_BITS 3
137#define __Vendor_SysTickConfig 0
140#define RCOSC48M_FREQ 48000000
141#define RCOSC24M_FREQ 24000000
146#ifdef CPU_VARIANT_X2
147#include <core_cm4.h>
148#else
149#include <core_cm3.h>
150#endif
157#define FLASH_BASE 0x00000000
158#define PERIPH_BASE 0x40000000
159#define PERIPH_BASE_NONBUF 0x60000000
160#define ROM_HARD_API_BASE 0x10000048
161#define ROM_API_TABLE ((uint32_t *) 0x10000180)
168#define ADI_DIR 0x00000000
169#define ADI_SET 0x00000010
170#define ADI_CLR 0x00000020
171#define ADI_MASK4B 0x00000040
172#define ADI_MASK8B 0x00000060
173#define ADI_MASK16B 0x00000080
176#ifdef __cplusplus
177}
178#endif
179
180#endif /* CC26XX_CC13XX_H */
volatile uint32_t reg32_t
Unsigned 32-bit register type.
reg16_t reg8_m8_t
Masked 8-bit register.
volatile uint16_t reg16_t
Unsigned 16-bit register type.
enum IRQn IRQn_Type
Interrupt number definition.
volatile uint8_t reg8_t
Unsigned 8-bit register type.
@ PendSV_IRQn
14 Cortex-M4 Pend SV Interrupt
@ GPTIMER_0B_IRQN
32 Timer 0 subtimer B
@ UART0_IRQN
21 UART0 Rx and Tx
@ GPTIMER_2A_IRQN
35 Timer 2 subtimer A
@ AUX_ADC_IRQN
48 AUX ADC IRQ
@ GPTIMER_2B_IRQN
36 Timer 2 subtimer B
@ RF_CPE1_IRQN
18 RF Command and Packet Engine 1
@ AON_AUX_SWEV0_IRQN
22 Sensor Controller software event 0, through AON domain
@ GPTIMER_0A_IRQN
31 Timer 0 subtimer A
@ AUX_COMBO_IRQN
44 AUX combined event, directly to MCU domain
@ WATCHDOG_IRQN
30 Watchdog timer
@ MemoryManagement_IRQn
4 Cortex-M4 Memory Management Interrupt
@ AON_RTC_IRQN
20 AON RTC
@ PROG_IRQN
46 Dynamic Programmable interrupt (default source: PRCM)
@ GPTIMER_3A_IRQN
37 Timer 3 subtimer A
@ IRQN_COUNT
Number of peripheral IDs.
@ I2S_IRQN
28 I2S
@ SVCall_IRQn
11 Cortex-M4 SV Call Interrupt
@ FLASH_CTRL_IRQN
42 Flash controller
@ GPTIMER_3B_IRQN
38 Timer 3 subtimer B
@ UDMA_ERR_IRQN
41 uDMA Error
@ UsageFault_IRQn
6 Cortex-M4 Usage Fault Interrupt
@ SSI1_IRQN
24 SSI1 Rx and Tx
@ SysTick_IRQn
15 Cortex-M4 System Tick Interrupt
@ ResetHandler_IRQn
1 Reset Handler
@ AUX_COMPA_IRQN
47 AUX Comparator A
@ BusFault_IRQn
5 Cortex-M4 Bus Fault Interrupt
@ I2C_IRQN
17 I2C
@ RF_HW_IRQN
26 RF Core Hardware
@ DebugMonitor_IRQn
12 Cortex-M4 Debug Monitor Interrupt
@ RF_CPE0_IRQN
25 RF Command and Packet Engine 0
@ RF_CMD_ACK_IRQN
27 RF Core Command Acknowledge
@ UDMA_IRQN
40 uDMA Software
@ EDGE_DETECT_IRQN
16 AON edge detect
@ PKA_IRQN
19 PKA interrupt
@ SW0_IRQN
43 Software Event 0
@ HardFault_IRQn
3 Cortex-M4 Hard Fault Interrupt
@ GPTIMER_1B_IRQN
34 Timer 1 subtimer B
@ CRYPTO_IRQN
39 Crypto Core Result available
@ GPTIMER_1A_IRQN
33 Timer 1 subtimer A
@ AON_PRG0_IRQN
45 AON programmable 0
@ SSI0_IRQN
23 SSI0 Rx and Tx
@ NonMaskableInt_IRQn
2 Non Maskable Interrupt
@ AON_AUX_SWEV1_IRQN
29 Sensor Controller software event 1, through AON domain
@ TRNG_IRQN
49 TRNG event
IRQn
Interrupt Number Definition.
Definition cc2538.h:35
Masked 32-bit register.
reg32_t HIGH
High 16-bit half.
reg32_t LOW
Low 16-bit half.
Masked 8-bit register.
reg8_t HIGH
High 4-bit half.
reg8_t LOW
Low 4-bit half.