Loading...
Searching...
No Matches
cfg_usb_otg_hs_phy_utmi.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2019 Koen Zandberg
3 * 2022 Gunar Schorcht
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
25#ifndef CFG_USB_OTG_HS_PHY_UTMI_H
26#define CFG_USB_OTG_HS_PHY_UTMI_H
27
28#include "periph_cpu.h"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
38#define DWC2_USB_OTG_HS_ENABLED
39
40#ifndef USBPHYC_TUNE_VALUE
54#define USBPHYC_TUNE_VALUE 0x00000f13U
55#endif
56
61 {
62 .periph = USB_OTG_HS_PERIPH_BASE,
63 .type = DWC2_USB_OTG_HS,
65 .rcc_mask = RCC_AHB1ENR_OTGHSEN,
66 .irqn = OTG_HS_IRQn,
67 .ahb = AHB1,
68 .dm = GPIO_PIN(PORT_B, 14),
69 .dp = GPIO_PIN(PORT_B, 15),
70 .af = GPIO_AF10,
71 .phy_tune = USBPHYC_TUNE_VALUE,
72 }
73};
74
78#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
79
80#ifdef __cplusplus
81}
82#endif
83
84#endif /* CFG_USB_OTG_HS_PHY_UTMI_H */
@ PORT_B
port B
Definition periph_cpu.h:48
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define USBPHYC_TUNE_VALUE
Default value of USBPHYC tuning control register.
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG HS configuration.
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:113
uintptr_t periph
USB peripheral base address.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_UTMI
UTMI for internal HS PHY.
@ DWC2_USB_OTG_HS
High speed peripheral.